High Speed Matrix Multiplication Implementation Using Field Programmable Gate Array

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2014 by IJETT Journal
Volume-7 Number-2                          
Year of Publication : 2014
Authors : Shriyashi Jain , Neeraj Kumar , Jaikaran Singh , Mukesh Tiwari
  10.14445/22315381/IJETT-V7P221

citation 

Shriyashi Jain , Neeraj Kumar , Jaikaran Singh , Mukesh Tiwari , Article:High Speed Matrix Multiplication Implementation Using Field Programmable Gate Array, International Journal of Engineering Trends and Technology(IJETT), 7(2),75-78, published by seventh sense research group

Abstract

Matrix operations are commonly used in almost all areas of scientific research. Matrix multiplication has significant application in the areas of graph theory, numerical algorithms, signal processing, and digital control. Matrix multiplication is a computationally intensive problem, especially the design and efficient implementation on an FPGA where resources are very limited, has been more demanding. In this paper, we implement an architecture that is capable of handling matrices of variable sizes. This design minimize the gate count, area, improvements in latency, computational time, throughput for performing matrix multiplication and reduce the number of multiplication and additions hardware required to get the matrices multiplied on commercially available FPGA devices. The hardware design in our work to multiply two numbers is use the multiplier unit used for multiplying two numbers in a single clock cycle. This increases the speed of the computation. The system is simple to implement and is highly scalable, the system can be scaled with simple repetition of the hardware and with no changes in the algorithm. Our approach converts matrix multiplication in programmable processors into a computation channel, when increasing the processing throughput, the output noise (error) increases due to computational errors caused by exceeding the machine-precision limitations.

References

[1] Shu-Qing Li, Chi Hou Chan, Leung Tsan "Parallel Implementation of the Sparse-Matrix/Canonical Grid Method for the Analysis of Two-Dimensional Random Rough Surfaces (Three-Dimensional Scattering Problem) on a Beowulf System" IEEE Transactions On Geoscience And Remote Sensing, Vol. 38, No. 4, July 2000

[2] Nan Zhang "A Novel Parallel Scan for Multicore Processors and Its Application in Sparse Matrix-Vector Multiplication" IEEE Transactions On Parallel And Distributed Systems, Vol. 23, No. 3, March 2012

[3] Bahram Hamraz, Nicholas HM Caldwell, and P. John Clarkson "A Matrix-Calculation-Based Algorithm for Numerical Change Propagation Analysis" IEEE Transactions On Engineering Management, Vol. 60, No. 1, February 2013

[4] Vasileios Karakasis, Theodoros Gkountouvas, Kornilios Kourtis, Georgios Goumas, Nectarios Koziris "An Extended Compression Format for the Optimization of Sparse Matrix-Vector Multiplication" IEEE Transactions On Parallel And Distributed Systems- 2013.

Keywords:
Multiplier, Xilinx Software, Vhdl Language, FPGA, Latency.