Double Precision Floating Point Square Root Computation

Double Precision Floating Point Square Root Computation

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2014 by IJETT Journal
Volume-13 Number-6
Year of Publication : 2014
Authors : Najib Ghatte , Shilpa Patil , Deepak Bhoir
  10.14445/22315381/IJETT-V13P259

Citation 

Najib Ghatte , Shilpa Patil , Deepak Bhoir. "Double Precision Floating Point Square Root Computation ", International Journal of Engineering Trends and Technology (IJETT), V13(6),294-298 July 2014. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

Abstract

Square Root operation has found its prominence in many digital signal processing but it is very elusive to implement on FPGA due to its complicated computations. Many iterative algorithms which include restoring and non-restoring algorithms, SRT were proposed. Most of them implement with slow or large components which are less suitable for real-time applications than the addition or multiply components. This paper deals with the novel algorithm of square root computation of double precision floating point division. Verilog Code is written and implemented on Virtex-5 FPGA series.

References

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Keywords
Double precision, Binary square root, Vedic, Virtex, FPGA, Dvanda, IEEE-754.