Analysis and Design of Positive Feedback Adiabatic Logic (PFAL) Based Universal Gates

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2016 by IJETT Journal
Volume-33 Number-1
Year of Publication : 2016
Authors : Sowmiya.M, Darwin.S, Sindhuja.D, Sheela Merlin.M
  10.14445/22315381/IJETT-V33P202

MLA 

Sowmiya.M, Darwin.S, Sindhuja.D, Sheela Merlin.M"Analysis and Design of Positive Feedback Adiabatic Logic (PFAL) Based Universal Gates", International Journal of Engineering Trends and Technology (IJETT), V33(1),4-7 March 2016. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

Abstract
This paper presents positive feedback adiabatic logic that employs the principle of adiabatic charge recovery. The low power PFAL apply a sinusoidal power supply with magnitude Vdd. Dynamic power contributes large power in hardware design. So the design of a circuit with less power consumption for low power application has become critical concern. More energy is dissipated during the switching events. PFAL circuit dramatically reduces power dissipation by reducing switching activity. This paper also analysis the design of NAND, NOR, NOT logic gate based on PFAL topology. The simulation result is obtained using Tanner EDA Tools. Positive Feedback Adiabatic Logic contributes the best way to reuse the energy stored at the output node capacitor instead of discharging it to the ground node.

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Keywords
Adiabatic logic, dynamic power, PFAL, low power, switching activity.