Analysis and Design of Positive Feedback Adiabatic Logic (PFAL) Based Universal Gates

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
© 2016 by IJETT Journal
Volume-33 Number-1
Year of Publication : 2016
Authors : Sowmiya.M, Darwin.S, Sindhuja.D, Sheela Merlin.M


Sowmiya.M, Darwin.S, Sindhuja.D, Sheela Merlin.M"Analysis and Design of Positive Feedback Adiabatic Logic (PFAL) Based Universal Gates", International Journal of Engineering Trends and Technology (IJETT), V33(1),4-7 March 2016. ISSN:2231-5381. published by seventh sense research group

This paper presents positive feedback adiabatic logic that employs the principle of adiabatic charge recovery. The low power PFAL apply a sinusoidal power supply with magnitude Vdd. Dynamic power contributes large power in hardware design. So the design of a circuit with less power consumption for low power application has become critical concern. More energy is dissipated during the switching events. PFAL circuit dramatically reduces power dissipation by reducing switching activity. This paper also analysis the design of NAND, NOR, NOT logic gate based on PFAL topology. The simulation result is obtained using Tanner EDA Tools. Positive Feedback Adiabatic Logic contributes the best way to reuse the energy stored at the output node capacitor instead of discharging it to the ground node.


1) Prasad D Khandekar, Shaila Subbaraman, and Abhijit V. Chitre Implementation and Analysis of Quasi-Adiabatic Inverters International conference of engineers and computer Scientist 2010 Vol II IMECS 17-19-201 Hong Kong
2) Arsalan, Shams, “Charge-recovery power clock generators for adiabatic logic circuits”, 18th International Conference on VLSI Design, pp. 171- 174, 3-7 January 2005.
3) Indermauer.T and Horowitz.M, “Evaluation of Charge Recovery Circuits and Adiabatic Switching for Low Power Design, “Technical Digest IEEE Sym.Low Power Electronics, San Diego, pp. 102-103, Oct. 2002.
4) Mukesh Tiwari, Jai karan Singh, Yashasvi Vaidhya “Adiabatic Positive Feedback Charge Recovery Logic for low power CMOS Design” IJCTEE, Volume 2, Issue 5, October 2012.
5) Prof Mukesh Tiwari, Prof Jaikaran Singh, Mr Yashasvi Vaidhya “Adiabatic Improved Efficient Charge Recovery Logic for low power CMOS logic ” International journal of Electronic Communication and Computer Engineering pp 350-354 Vol 1 issue 5.
6) Samik Samanta Power Efficient VLSI Inverter Design using Adiabatic Logic and Estimation of Power dissipation using VLSI-EDA Tool Special Issue of IJCCT Vol. 2 Issue 2, 3, 4; 2010 for International Conference [ICCT-2010], 3rd-5th December 2010
7) nand-xor-xnor-gates-35078548?qid=8f8afd9a-7415- 4e83-b2b6-dcabda54efc8&v=&b=&from_search=1
8) W.C. Athas, L.J. Svensson, J.G. Koller, N.Tzartzains, and E. Y-C. Chou, “Low-power digital systems based on adiabatic-switching principles,”Very Large Scale Integration. (VLSI) Syst., IEEE Transaction on, Vol.2, Issue4, Dec., 1994, pp.398-407.
9) Sonal Jain, Prof. Monika Kapoor,” Design and Analysis of CMOS and Adiabatic 4-Bit Binary Multiplier” International Journal of Engineering Trends and Technology (IJETT) – Volume 7 Number 2 - Jan 2014
10) B. Dilli Kumar, M. Bharathi “Design of Energy Efficient Arithmetic Circuits Using Charge Recovery Adiabatic Logic” International Journal of Engineering Trends and Technology- Volume4Issue1- 2013

Adiabatic logic, dynamic power, PFAL, low power, switching activity.