Design of 32 Bit Low Power RISC Processor for DSP Applications

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2016 by IJETT Journal
Volume-34 Number-1
Year of Publication : 2016
Authors : K.Hari Priya, Chinthakindi Roja Sree
  10.14445/22315381/IJETT-V34P202

MLA 

K.Hari Priya, Chinthakindi Roja Sree"Design of 32 Bit Low Power RISC Processor for DSP Applications", International Journal of Engineering Trends and Technology (IJETT), V34(1),5-14 April 2016. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

Abstract
In this paper, Implementation of 32 bit low power Five stage pipelining RISC processor using Harvard architecture for DSP applications is presented. To achieve low power, architecture modifications are made in the incrementer circuit by using binary excess converter (BEC) instead of ripple carry adder, in arithmetic and logic unit (ALU) multiplier and adder is designed by using modified Wallace tree with common Boolean logic and carry select adder (CSLA) using common Boolean logic(CBL).In order to use processor for DSP applications multiply and accumulator unit (MAC) unit is designed.FIR filter application is developed by using designed RISC processor. This project is implemented on Sparten3 Xilinx FPGA board by using verilog, Xilinx 13.2 ISE simulator and XST is used for simulation and synthesis. On chip functionality verified by chip scope pro analyzer and power is analyzed by Xpower analyzer. Result analysis shows that power as been reduced from 532.82mw to 105.18mw.

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Keywords
Reduced instruction set computer (RISC), Arithmetic and logic unit (ALU), Binary to excess converter(BEC),Common Boolean logic (CBL), Digital signal processing (DSP),finite impulse response (FIR).