Design of 32 Bit Low Power RISC Processor for DSP Applications

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
© 2016 by IJETT Journal
Volume-34 Number-1
Year of Publication : 2016
Authors : K.Hari Priya, Chinthakindi Roja Sree


K.Hari Priya, Chinthakindi Roja Sree"Design of 32 Bit Low Power RISC Processor for DSP Applications", International Journal of Engineering Trends and Technology (IJETT), V34(1),5-14 April 2016. ISSN:2231-5381. published by seventh sense research group

In this paper, Implementation of 32 bit low power Five stage pipelining RISC processor using Harvard architecture for DSP applications is presented. To achieve low power, architecture modifications are made in the incrementer circuit by using binary excess converter (BEC) instead of ripple carry adder, in arithmetic and logic unit (ALU) multiplier and adder is designed by using modified Wallace tree with common Boolean logic and carry select adder (CSLA) using common Boolean logic(CBL).In order to use processor for DSP applications multiply and accumulator unit (MAC) unit is designed.FIR filter application is developed by using designed RISC processor. This project is implemented on Sparten3 Xilinx FPGA board by using verilog, Xilinx 13.2 ISE simulator and XST is used for simulation and synthesis. On chip functionality verified by chip scope pro analyzer and power is analyzed by Xpower analyzer. Result analysis shows that power as been reduced from 532.82mw to 105.18mw.


[1] Samiappa Sakthikumaran et al,”A Very Fast and Low Power Incrementer and Decrementer Circuits”, International Journal of Computer Communication and Information System(IJCCIS) Vol2. No.1 – 2011.
[2] B. Ramkumar and Harish M Kittur, “Low power and area efficient carry select adder”, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no. 2, pp. 371-375, Feb 2012.
[3] Pallavi Saxena1, Urvashi Purohit2, Priyanka Joshi3,”Analysis of Low Power, Area- Efficient and HighSpeed Fast Adder”, International Journal of Advanced Research in Computer and Communication Engineering Vol. 2, Issue 9, September 2013 Copyright to IJARCCE 3705.
[4] HimanshuBansal, K. G. Sharma, Tripti SharmaECE department, MUST University, Lakshmangarh, Sikar, Rajasthan, India,”Wallace Tree Multiplier Designs: A Performance Comparison Review”,Innovative Systems Design and Engineering www.iiste.orgISSN 2222-1727 (Paper) ISSN 2222-2871 (Online) Vol.5, No.5, 2014.
[5] Damarlaparadhasaradhi,m.prashanthi and N.vivek, ”Modified wallace tree multiplier using efficient square root carry select adder”,IEEE,2014.
[6] Samiappa Sakthikumaran, S. Salivahanan, V. S. Kanchana Bhaaskaran,”16-Bit RISC Processor Design for Convolution Application”, IEEE-International Conference on Recent Trends in Information Technology. June 3-5, 2011.
[7] HE Jing-yu, LI Li-li, ZHU Yan-chao, YANG Wen-tao, and YANG Jian-hong ,”Multiply-Accumulator Using Modified Booth Encoders Designed for Application in16-bit RISC Processor”,©2013 IEEE,2nd International Symposium on Instrumentation and Measurement, Sensor Network and Automation (IMSNA).

Reduced instruction set computer (RISC), Arithmetic and logic unit (ALU), Binary to excess converter(BEC),Common Boolean logic (CBL), Digital signal processing (DSP),finite impulse response (FIR).