Design and Implementation of Bit Error Rate Tester on FPGA for Spacecraft Data Acquisition System

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
© 2016 by IJETT Journal
Volume-36 Number-2
Year of Publication : 2016
Authors : Sinchana B, Unnikrishnan P, M Kavitha, Suguna G C


Sinchana B, Unnikrishnan P, M Kavitha, Suguna G C"Design and Implementation of Bit Error Rate Tester on FPGA for Spacecraft Data Acquisition System", International Journal of Engineering Trends and Technology (IJETT), V36(2),97-101 June 2016. ISSN:2231-5381. published by seventh sense research group

Bit Error Rate (BER) is a measure of performance of a data transmission medium. BERT is used to decide the integrity of a system i.e., how effectively it can transmit or receive data without introducing much error. The proposed device integrates the fundamental baseband modules on a single FPGA. BER tester consists of a Pattern Generator and an Analyzer that can be set to the same pattern. The payload data transmitted from the spacecraft consists of multiple channels per carrier based on modulation scheme. The available commercial equipments can calculate the Bit Error Rate for only one channel at a time. In order to support multichannel BER analysis, a Personal Computer (PC) based system is designed and implemented in Altera Stratix V (5SGSMD5K2F40C2) FPGA. A Graphical User Interface (GUI) is developed to observe the Bit Error Rate and other parameters. In the proposed system, the BER of the Telemetry system is calculated using both PN and Gold sequences. The FPGA implementation of BERT is cost effective, flexible and is faster than software simulation methods.


[1] A. Alimohammad, S. F. Fard, and B. F. Cockburn, “FPGA-based accelerator for the verification of leadingedge wireless systems,” in Proc.IEEE Int DAC,Jul 2009.
[2] “Design and Implementation of BER Tester on FPGA for FSO communication Systems” K.Vinoth, K.S.Vinodhini. SSRG International Journal of Electronics and Communication Engineering (SSRGIJECE) volume 2 Issue 3 March 2015.
[3] “FPGA-Based Bit Error Rate Performance measuring of Wireless Systems”. Viha Pataskar , Vishal Puranik, International Journal of Innovative Research in Science, Engineering and Technology, May 2015.
[4] Peter J. Smith, Mansoor Sha_ and Hongsheng Gao, “Quick sim-ulation: A review of importance sampling techniques in communication systems,” IEEE Journal on Selected Areas in Communications, vol. 15, May 1997.
[5] “FPGABased Bit Error Rate Performance Measurement of Wireless Systems”, Ali Mohammad. A. Fard, S.F. Very Large Scale Integration (VLSI) Systems, IEEE Transactions 2014.
[6] “Bit error rate testing scheme for digital communication devices”. Marda, N; Vaishnav.G; Control, Instrumentation, Energy and Communication (CIEC), 2014 International Conference.
[7] “Bit Error Rate Testing Serial Communication Equipment using Pseudo-Random Bit Sequences” Marius Strobl, Thomas Waas University of Applied Sciences Regensburg Regensburg, Germany Marcel Moolenaar Juniper Networks, Inc. Sunnyvale, CA, USA Angelika Schingale, Norbert Balbierer, 2012.
[8] Stratix V Device Handbook, Altera Corporation, Vol. 1.

Telemetry, Bit Error Rate Tester, Linear Feedback Shift Register (LFSR), Altera Stratix V, Altera Quartus II 14.0.