Design and Implementation of Bit Error Rate Tester on FPGA for Spacecraft Data Acquisition System

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2016 by IJETT Journal
Volume-36 Number-2
Year of Publication : 2016
Authors : Sinchana B, Unnikrishnan P, M Kavitha, Suguna G C
  10.14445/22315381/IJETT-V36P218

MLA 

Sinchana B, Unnikrishnan P, M Kavitha, Suguna G C"Design and Implementation of Bit Error Rate Tester on FPGA for Spacecraft Data Acquisition System", International Journal of Engineering Trends and Technology (IJETT), V36(2),97-101 June 2016. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

Abstract
Bit Error Rate (BER) is a measure of performance of a data transmission medium. BERT is used to decide the integrity of a system i.e., how effectively it can transmit or receive data without introducing much error. The proposed device integrates the fundamental baseband modules on a single FPGA. BER tester consists of a Pattern Generator and an Analyzer that can be set to the same pattern. The payload data transmitted from the spacecraft consists of multiple channels per carrier based on modulation scheme. The available commercial equipments can calculate the Bit Error Rate for only one channel at a time. In order to support multichannel BER analysis, a Personal Computer (PC) based system is designed and implemented in Altera Stratix V (5SGSMD5K2F40C2) FPGA. A Graphical User Interface (GUI) is developed to observe the Bit Error Rate and other parameters. In the proposed system, the BER of the Telemetry system is calculated using both PN and Gold sequences. The FPGA implementation of BERT is cost effective, flexible and is faster than software simulation methods.

 References

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Keywords
Telemetry, Bit Error Rate Tester, Linear Feedback Shift Register (LFSR), Altera Stratix V, Altera Quartus II 14.0.