A Efficient Low-Power High Speed Digital Circuit Design by using 1-bit GDI Full Adder Circuit
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International Journal of Engineering Trends and Technology (IJETT) |  |
| © 2016 by IJETT Journal | ||
| Volume-36 Number-3 |
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| Year of Publication : 2016 | ||
| Authors : Rohit Tripati, Paresh Rawat |
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| DOI : 10.14445/22315381/IJETT-V36P229 |
Citation
Rohit Tripati, Paresh Rawat"A Efficient Low-Power High Speed Digital Circuit Design by using 1-bit GDI Full Adder Circuit", International Journal of Engineering Trends and Technology (IJETT), V36(3),155-160 June 2016. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
Abstract
To achieve low power consumption with less area, static CMOS logic styles has become the most suitable design approach for the past three decades. New designs of GDI based basic digital (AND, OR, XOR) gates are presented using single pass transistors to improve proper swing level of the output waveform of GDI gates. The new design of basic gates with combination pass transistor and GDI logic form a hybrid GDI technique. In such designs of hybrid GDI gates, pass transistors are activated only in cases where threshold drop occurs at the output. In this paper we presented a new 13T full adder design based on hybrid –CMOS logic design style. Proposed new design is compared with some existing designs for power consumption, delay, PDP at various frequencies viz 10 MHz, 300 MHz and 1 GHz. From the simulation results, it is observed that, hybrid GDI based digital circuits consumes less power, delay and area as compared to static CMOS based circuits. Proposed technique shows less power dissipation and less propagation delay as compared to existing GDI technique with slight increase in area. it shows less power and less delay with about 60% area increase as compared to basic GDI.
References
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Keywords
C-CMOS, CPL, Hybrid Adder, GDI, Floating adder.