A Power and Area Efficient Design of an 8-Bit Priority Encoder using 45nm Technology

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
© 2016 by IJETT Journal
Volume-36 Number-4
Year of Publication : 2016
Authors : Akhil Arora, Rajesh Mehra


Akhil Arora, Rajesh Mehra"A Power and Area Efficient Design of an 8-Bit Priority Encoder using 45nm Technology", International Journal of Engineering Trends and Technology (IJETT), V36(4),184-187 June 2016. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

The previous priority encoder circuits which faced problems like race conditions and charge sharing are eliminated by the proposed Priority Encoder. The main objective of the paper is to compare the power consumption and area of an 8 bit priority encoder in Semi-custom and Full-custom design. The power consumption in full custom has significantly reduced by 1.06 μW and design area has been reduced by 12.5 μm2. This paper shows improvement in design of the priority encoder up to 19.7% in power and 13.5% in area.


[1] Amritesh Ojha and Rajesh Mehra “Low Power Layout Designof Priority Encoder Using 65nm Technology”, International Journal of Engineering Trends and technology, Vol. 23, Number 9, pp 450-453, 2015.
[2] Xiaoyu Wang and Yukang Feng “AnalysisandDesignof8- BitCMOSPriorityEncoders”
[3] Richa Singh and Rajesh Mehra “Power Efficient Design Of Multiplexer Using Adiabatic Logic”, International Journal of advances in engineering and technology, Vol. 6, Issue 1, pp 246-254, 2013.
[4] K. Purnima, S. AdiLakshmi, M. Sahithi, A. Jhansi Rani, J. Poornima, “Design of Modified Shannon Based Full Adder Cell Using PTL Logic for Low Power Applications”, International Journal of Computer Science and Information Technologies, (IJCSIT) ,Vol. 3, No.1, pp. 2964-2968, 2012.
[5] Meena aggrawal , Aastha agrawal, Mr. Rajesh Mehra “4 Input decimal adder using 90 nm CMOS technology” IOSR Jouenal of Engineering, Vol. 3, pp-48-51, 2013.
[6] D. Markovic, B. Nikolic, V.G. Oklobdzija, “A General Method In Synthesis of Pass-Transistor Circuits”, ELSEVIER, Microelectronics Journal 31(11), pp. 991-998, 2000.
[7] Akhilesh Verma, Rajesh Mehra, “Design and Analysis of Conventional and Ratioed Cmos Logic Circuit”, IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Vol. 2, Issue 2, pp. 25-29, 2013.
[8] Pushpa Saini, Rajesh Mehra, “Leakage Power Reduction in CMOS VLSI Circuits”, International Journal of Computer Applications, Vol. 55, No. 8, pp. 42-48, 2012.
[9] Mariem Slimani, Philippe Matherat, “Multiple Threshold Voltage for Glitch Power Reduction”, IEEE Journal of Faible Tension Faible Consommation, Vol. 41, No 12, pp.67-70, 2011.
[10] R Mehra, S Devi, “ FPGA Implementation of High Speed Pulse Shaping Filter For SDR Applications”, International Conferences, NeCoM 2010, pp. 214-222, 2010.
[11] B. Dilli Kumar, A. Chandra Babu, V. Prasad, “ A Comparative Analysis of Low Power and Area Efficient Digital Circuit Design”, International Journal of Computer Technology and Applications, Vol 4 (5), pp 764-768, Sep-Oct 2013
[12] R Verma, R Mehra, “CMOS based design simulation Adder/Subtractor using different foundries”, National conference on Recent Advances on Electronics and Communication Engineering, pp 1-7, Mar 2014
[13] Chiraz Khedhiri, Mouna Karmani, Belgacem Hamdi, Ka Lok Man, Yue Yang and Lixin Cheng, “A Self-checking CMOS Full adder in Double Pass Transistor Logic”, International MultiConference of Engineers and Computer Scientists, vol2, Mar 2012.
[14] A. Shrama, R singh, R Mehra, “Low Power TG full adder design using CMOS nano technology, Parallel Distributed and Grid Computing, IEEE 2nd International Conference, pp 310- 213, Dec 2012.

Priority Encoder, VLSI, CMOS, Low power design, look ahead scheme.