A Power and Area Efficient Design of an 8-Bit Priority Encoder using 45nm Technology

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2016 by IJETT Journal
Volume-36 Number-4
Year of Publication : 2016
Authors : Akhil Arora, Rajesh Mehra
  10.14445/22315381/IJETT-V36P234

MLA 

Akhil Arora, Rajesh Mehra"A Power and Area Efficient Design of an 8-Bit Priority Encoder using 45nm Technology", International Journal of Engineering Trends and Technology (IJETT), V36(4),184-187 June 2016. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

Abstract
The previous priority encoder circuits which faced problems like race conditions and charge sharing are eliminated by the proposed Priority Encoder. The main objective of the paper is to compare the power consumption and area of an 8 bit priority encoder in Semi-custom and Full-custom design. The power consumption in full custom has significantly reduced by 1.06 μW and design area has been reduced by 12.5 μm2. This paper shows improvement in design of the priority encoder up to 19.7% in power and 13.5% in area.

 References

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Keywords
Priority Encoder, VLSI, CMOS, Low power design, look ahead scheme.