Optimized Design and Simulation of Ring Counter using 45nm Technology

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
© 2016 by IJETT Journal
Volume-36 Number-4
Year of Publication : 2016
Authors : Sandeep Thakur, Rajesh Mehra


Sandeep Thakur, Rajesh Mehra"Optimized Design and Simulation of Ring Counter using 45nm Technology", International Journal of Engineering Trends and Technology (IJETT), V36(4),188-193 June 2016. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

In the era of technical world, sequential circuits are playing their vital role in the designing of digital system. Sequential circuit design with low power and high speed at smaller chip size has become the prime concern for researcher and day by day growth in VLSI technologies also sustain the flow for achieving the desired goals. A counter is a sequential circuit having various applications in the field of embedded system, pattern generations, signal synthesis, Digital to Analog conversion etc. In this paper, an optimized designing mechanism has been deployed to design a high speed, cost effective and low power 4-bit ring counter which can also be extended to higher order ring counter designs. In this work, performance of the proposed ring counter is enhanced by using a negative edge triggered master slave D flip flop which have 14 MOS transistors in its design as compare to conventional counter. The proposed paper has accomplished the design goals by reducing the 68.5% transistor count, 29.85% power consumption and got the 95% higher speed.


[1] Yogita Hiremath, Akalpita L. Kulkarni, J. S. Baligar, “Design and Implementation of Synchronous 4-Bit Up Counter Using 180 nm CMOS Process Technology”, International Journal of Research in Engineering and Technology (IJRET), Vol. 3, No. 5, pp. 810-815, May 2014.
[2] B.R.B Jaswanth, R.V.S Rayudu, K.Mani babu, R.Himaja, L.Veda kumar, “A Design Of A Low Power Delay Buffer Using Ring Counter Addressing Schemes,” International Journal of Technological Exploration and Learning, Vol. 2, Issue. 2, pp. 99-103, April 2013.
[3] Wayne Wolf, Modern VLSI Design, 3rd ed., Pearson Education, 2007, pp. 22-27.
[4] Upwinder Kaur, Rajesh Mehra “Low Power CMOS Counter Using Clock Gated Flip-Flop”, International Journal of Engineering and Advanced Technology (IJEAT), Volume-2, Issue-4, pp. 796-798, April 2013.
[5] Sani M. Ismail, Saadmaan Rahman, Neelanjana S. Ferdous “A Design Scheme of Toggle Operation Based Ring Counter with Efficient Clock Gating”, IEEE International conference on Computational Intelligene, Modelling and Simulation, pp. 393-399, 2012
[6] Neil H. E. Weste, David Harris and Ayan Banerjee, CMOS VLSI Design, 3rd edition, 2006 pp. 4-10.
[7] Ankita Mahajan, Rajesh Mehra, “Area Efficient CMOS Layout Design of Ring Counter”, International Journal of Scienticfic Research Engineering and Technology (IJSRET), pp 169-172, March 2015..
[8] Pushpa Saini, Rajesh Mehra, “Leakage Power Reduction in CMOS VLSI Circuits”, International Journal of Computer Applications, Vol. 55, No. 8, pp. 42-48, october 2012.
[9] Rishikesh V. Tambat, Sonal A. Lakhotiya, “Design of Flip- Flops for High Performance VLSI Applications using Deep Submicron CMOS Technology” International Journal of Current Engineering and Technology, Vol 4, No. 2, pp. 769- 774, March 2014

Ring Counter; Master slave D flip flop; negative Edge trigged; VLSI power dissipation; Transistor count;CMOS gates.