Power and Area Efficient CMOS Half Adder using GDI Technique

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
© 2016 by IJETT Journal
Volume-36 Number-8
Year of Publication : 2016
Authors : Ranbirjeet Kaur, Rajesh Mehra


Ranbirjeet Kaur, Rajesh Mehra"Power and Area Efficient CMOS Half Adder using GDI Technique", International Journal of Engineering Trends and Technology (IJETT), V36(8),401-405 June 2016. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

In the modern era minimizing power consumption for digital systems involves optimization at all levels of the design and power dissipation has become a major and vital constraint in industries. Different techniques are applied to reduce the power dissipation. A novel Gate-diffusion input (GDI) circuits are applied to different logical circuits.GDI technique reduces the power consumption to greater extent as compared to other techniques. This technique also reduce the number of transistors used, hence reduce the area.GDI cell has same structure as that of CMOS transistor with low complexity and low switching transition.GDI technique also provides enhanced hazard tolerance and are more suitable for low Voltage operations. In this paper half adder with GDI technique is presented and comparison has been done in terms of no. of transistors and power dissipation with other half adders using other techniques. The Main aim of this paper is to de Half adder with GDI technique is 30% faster, and consume 85% less power.


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GDI, Transmission gate, CMOS, Power dissipation.