Power and Area Efficient CMOS Half Adder using GDI Technique

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2016 by IJETT Journal
Volume-36 Number-8
Year of Publication : 2016
Authors : Ranbirjeet Kaur, Rajesh Mehra
  10.14445/22315381/IJETT-V36P274

MLA 

Ranbirjeet Kaur, Rajesh Mehra"Power and Area Efficient CMOS Half Adder using GDI Technique", International Journal of Engineering Trends and Technology (IJETT), V36(8),401-405 June 2016. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

Abstract
In the modern era minimizing power consumption for digital systems involves optimization at all levels of the design and power dissipation has become a major and vital constraint in industries. Different techniques are applied to reduce the power dissipation. A novel Gate-diffusion input (GDI) circuits are applied to different logical circuits.GDI technique reduces the power consumption to greater extent as compared to other techniques. This technique also reduce the number of transistors used, hence reduce the area.GDI cell has same structure as that of CMOS transistor with low complexity and low switching transition.GDI technique also provides enhanced hazard tolerance and are more suitable for low Voltage operations. In this paper half adder with GDI technique is presented and comparison has been done in terms of no. of transistors and power dissipation with other half adders using other techniques. The Main aim of this paper is to de Half adder with GDI technique is 30% faster, and consume 85% less power.

 References

[1] Anjali Sharma, Rajesh Mehra” Area and Power Efficient CMOS Adder Design by Hybridizing PTL and GDI Technique”, International Journal of Computer Applications (0975 – 8887) Volume 66– No.4, March 2013
[2] A Sharma Singh, R Mehra,”Low power TG full adder design using CMOS nano technology”, parallel distributed and grid computing (PDGC), 2nd IEEE, pp.210-213,2012
[3] H. Bui, Y. Wang and Y. Jiang, “Design and Analysis of Low-Power 10-T Full Adders Using Novel XOR–XNOR Gates”, IEEE Transactions on Circuits and Systems Analog and Digital Signal Processing, Volume. 49, pp. 25-30, 2002.
[4]. Richa Singh and Rajesh Mehra, “Power efficient design of multiplexer using adiabatic logic”, International Journal of advances in engineering and technology, pp 247-254, March 2013.
[5]. Neil H.E.Weste, David Harris and Ayan Banaerjee, “CMOS VLSI design”. Pearson Education,Inc., pp. 11, Third Edition, 2005
[6] Ranjeeta Verma and Rajesh Mehra , “CMOS Based Design Simulation Of Adder /Subtractor Using Different Foundriess”, International Journal of Science and Engineering, Volume 2, Number 1 – 2013, pp. 28-34
[7] M. Shams, and M. A. Bayoumi, “A Novel High Performance CMOS 1-Bit Full Adder Cell”, IEEE Transactions on Circuit and System, Volume.47, NO. 5, May, 2000
[8] Y.Tau, D.A.Buchanan, W.Chen, D.Frank, K.Ismail, S.Lo, G.Sai-Halasz, R.Viswanathan, H.Wann, S.Wind, and H.Wong, “CMOS Scaling into the Nanometer Regime,” Proceeding of the IEEE, Volume.85, pp. 486–504, 1997.
[9]. Hanchate, N. Ranganathan “A new technique for leakage reduction in cmos circuits using selfcontrolled stacked transistors,” 17th International Conference on VLSI Design, pp.228-233.2004
[10]. W.Jyh-Ming. F.Sung-Chuan, and F.Wu-shiung, “New efficient designs for X-OR and XNOR functions on the transistor level,” solid-state circuits, IEEE journal, Of. Volume.29,pp.780-786,1994.
[11]. M. Morris Mano, Michael D. Cilleti “Digital Design”, 4th edition, pp.143, 2012.
[12] V. Elamaran, G. Rajkumar, S. Singh Rajpurohit and R. Anooj Krishnan, 2014. “Low Power Adder- Subtractor using Efficient XOR Gates.” Journal of Applied Sciences, Volume.14, pp. 1623-1627.
[13] Haghparast, M. and K. Navi, 2007, “Reversible full adder circuit for nanotechnology based systems” J. Applied Sci., Volume.7, pp. 3995-4000.
[14] Leblebici, Y. and S.M. Kang, 1999. “CMOS Digital Integrated Circuits”. 2nd Edition. McGraw Hill, Singapore.
[15] Ravi Kumar Anand, Kartar Singh, Pankaj Verma, Ashish Thakur,” Design of area and power efficient half adder using transmission gate “,International Journal of Research in Engineering and Technology Volume: 04 , April-2015
[16] A. Morgenshtein, A. Fish, I. A. Wagner, “Gate- Diffusion Input (GDI) – A Power Efficient Method for Digital Combinatorial Circuits,” to be published, IEEE Trans. On VLSI..

Keywords
GDI, Transmission gate, CMOS, Power dissipation.