Implementation of Frequency Down Converter using Multiplier free filter on FPGA
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International Journal of Engineering Trends and Technology (IJETT) |  |
| © 2012 by IJETT Journal | ||
| Volume-3 Issue-4 |
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| Year of Publication : 2012 | ||
| Authors : K.S.Sushmitha , G.Vimala Kumari |
Citation
K.S.Sushmitha , G.Vimala Kumari. "Implementation of Frequency Down Converter using Multiplier free filter on FPGA". International Journal of Engineering Trends and Technology (IJETT). V3(4):495-501 Jul-Aug 2012. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
Abstract
In a Communication system, especially in some applications where confidential data is to be communicated , wideband of signals are used. Also the bandwidth of the signal is frequently varied so that it is undetectable by the third person. In such cases to detect the signal a Wideband DDC with variable filter specification s is required. In this paper, an efficient way of designing and implementing a Wideband Digital down Converter has been discussed. Though the received signal is RF signal with high data rates an IF stage is used to frequency shift the signal to fixed IF which is the input to ADC. This is sa mpled and given as input to DDC. Signal extraction using DDC is presented in detail. It is shown that f il ter bandwidth varies by varies with decimation factor. Decimation range in this paper is 2 to 16384. Filtering is implemented in stages to obtain efficient response. Also, the reasons for choosing FPGA over ASSP’s to implement DD C are provided. Xilinx ISE 10.1 version software is used for simulating each block of DDC at system level testing and Chip Scope Pro Analyzer tool is used for board level testing. Vitex - 5 FPGA with speed - 2 is the hardware used for implementing the design .
References
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Keywords
Wideband Digital down converter, ADC, Base band signal , Decimation, ASSP, FPGA, System level testing, Board level testing.