A Darlington Pair Based CMOS Two Stage Operational Amplifier at 32nm Technology

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2017 by IJETT Journal
Volume-43 Number-1
Year of Publication : 2017
Authors : Vinamrata Yadav, Nikhil Saxena, Amit Rajput
DOI :  10.14445/22315381/IJETT-V43P209

Citation 

Vinamrata Yadav, Nikhil Saxena, Amit Rajput "A Darlington Pair Based CMOS Two Stage Operational Amplifier at 32nm Technology", International Journal of Engineering Trends and Technology (IJETT), V43(1),53-57 January 2017. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

Abstract
The low power chip designing is a field of immense interest to the technology for electronics chip designing industries. Operational amplifiers (Op-Amps) are an integral parts of many analog and mixed signal systems. There is need to investigate the performance of the forthcoming scaled channel length CMOS devices. In this work a two stage CMOS Operational Amplifier with gain boosting technique, Darlington pair is proposed. The proposed Op-Amp shows high gain as well as high CMRR with reduced leakage current and power supply. This amplifier is highly useful for wireless communication because of low power consumption, high bandwidth, high gain and high CMRR. The designed operational amplifier gain is 93 dB, Unity-Gain Bandwidth is 538 MHz, CMRR is 100dB, slew rate is 20.13V/µS, power dissipation is 10pW, leakage current is 2.17pA, phase margin is 86º, and settling time is 95ns. The designed circuit is simulated using H-Spice tool at 32nm technology.

 References

[1] Pandey A, Chakraborty S, Saw SK, Nath V. A Darlington Pair Transistor Based Operational Amplifier. In: Proceedings of 2015 Global Conference on Communication Technologies (GCCT 2015). ; 2015:273-276.
[2] Russell FA, Ragazzini JR, Randall RH. Analysis of Problems in Dynamics by Electronic Circuits *. IEEE. 1944:444-452.
[3] Razavi B. Design of Analog CMOS Integrated Circuits.; 2001.
[4] Valero MR, Celma S, Medrano N, Calvo B, Azcona C. An ultra low-power low-voltage class AB CMOS fully differential OpAmp. ISCAS 2012 - 2012 IEEE Int Symp Circuits Syst. 2012:1967-1970. doi:10.1109/ISCAS.2012.6271661.
[5] Mahattanakul J. Design Procedure for Two-Stage CMOS Operational Amplifiers Employing Current Buffer. IEEE Trans circuits Syst. 2005;52(11):766-770.
[6] Conference I, Engineering E, Mashhad HE. A 1.5 v High Swing Ultra Low-Power Two Stage CMOS OP-AMP in 0.18 µm Technology. In: 2010 2nd International Conference on Mechanical and Electronics Engineering (ICMEE 2010). Vol 1. ; 2010:68-71.
[7] Sankar PAG, Kumar KU. Design and analysis of two stage operational amplifier based on emerging sub-32nm technology. Proc Int Conf "Advanced Nanomater Emerg Eng Technol ICANMEET 2013. 2013;2(icanmeet):587-591. doi:10.1109/ICANMEET.2013.6609382.
[8] Centurelli F, Monsurrò P, Scotti G, Trifiletti A. A very low-voltage differential amplifier for opamp design. 2011 20th Eur Conf Circuit Theory Des ECCTD 2011. 2011;(ecctd):769-772. doi:10.1109/ECCTD.2011.6043846.
[9] Dai S, Cao X, Yi T, Hubbard AE, Hong Z. 1-V low-power programmable rail-to-rail operational amplifier with improved transconductance feedback technique. IEEE Trans Very Large Scale Integr Syst. 2013;21(10):1928-1935. doi:10.1109/TVLSI.2012.2220387.
[10] Atac A, Geller A, Wunderlich R, Heinen S. A low power high GBW Fully differential subthreshold CMOS Opamp for CT ?? Modulators. In: 7th Conference on Ph.D. Research in Microelectronics and Electronics, PRIME 2011 - Conference Proceedings. ; 2011:205-208. doi:10.1109/PRIME.2011.5966253.
[11] Singh S, Soni BB, Gour P. High Quality Factor Two Notch Low Noise Darlington Amplifier for Low Frequency Application. In: 2015 International Conference on Computer Communication and Informatics (ICCCI-2015). ; 2015:8-12.
[12] Kuo C, Chiou H, Chung H. An 18 to 33 GHz Fully-Integrated Darlington Power Amplifier With Guanella-Type Transmission-Line Transformers in 0.18 µm CMOS Technology. IEEE Microw Wirel COMPONENTS Lett. 2013;23(12):668-670.
[13] Elahl AMHS, Fahmi MME, Mohammad SN. Quantitative analysis of high frequency performance of modified Darlington pair. Solid State Electron. 2002;46:593-595.
[14] Upadhyay P, Ghosh S, Kar R, Mandal D, Ghoshal SP. Low Static and Dynamic Power MTCMOS Based 12T SRAM Cell for High Speed Memory System. In: 2014 11th International Joint Conference on Computer Science and Software Engineering (JCSSE). Vol 66. ; 2014:212-217.
[15] Hummouda S, Tawfik MS, Raguie HF. LOW VOLTAGE FULLY DIFFERENTIAL OPAMP WITH HIGH GAIN WIDE BANDWIDTH SUITABLE FOR SWITCHED CAPACITOR APPLICATIONS. IEEE. 2002:324-327.

Keywords
—Two Stage CMOS Operational Amplifier, Spice Tool, Darlington Pair, Gain, CMRR, Leakage Current, and Power Dissipation.