Reversible Binary and BCD Adder Using DR Gate

Reversible Binary and BCD Adder Using DR Gate

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2017 by IJETT Journal
Volume-45 Number-2
Year of Publication : 2017
Authors : Ruchika Likhar, Akanksha Sinha
DOI :  10.14445/22315381/IJETT-V45P211

Citation 

Ruchika Likhar, Akanksha Sinha " Reversible Binary and BCD Adder Using DR Gate ", International Journal of Engineering Trends and Technology (IJETT), V45(2),47-51 March 2017. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

Abstract
Reversible logic is becoming one of the most promising research areas in the past few years and has being found that it is applicable in several technologies; such as low power CMOS, nanotechnology and optical computing. This is relatively new and emerging area in the field of computation which taught for thinking about computation Quantum Computing will be a total change in which computer will operate and function. The reversible arithmetic circuits are efficient regarding number of reversible gates, delay and quantum cost. Optimized design of these adders gives efficient processors. In this work we propose optimized Binary adders and BCD adders with the use of DR gate . The main purposes of designing reversible logic are to decrease quantum cost, gate count and the number of garbage outputs. The main focus is to minimize the actual resources and which provide flexibility. The proposed architecture is implemented in VHDL language using Xilinx ISE 13.2 and then it is going to be implemented in FPGA.

 References

[1] M.A. Nielsen, I.L. Chuang, “Quantum Computation and Quantum Information,” Cambridge University Press p. 13, Cambridge, 2000
[2] R. Landauer, “Irreversibility and heat generation in the computational process,” IBM journal of research and development, vol. 5, issue 3, pp. 183–191, July 1961.
[3] R. Keyes, R. Landauer, “Minimal energy dissipation in logic,” IBM Journal of Research and Development, vol. 14, issue 2, pp. 153–157, Mar. 1970.
[4] C.H. Bennett, “Logical reversibility of computation,” IBM J. Res. Dev., vol. 17, issue 6, pp. 525–532, Nov. 1973.
[5] Gordon E. Moore, “Cramming More Components onto Integrated Circuits,” Electronics, pp. 114–117, April 19, 1965.
[6] F.Q. Xie, L. Nittel, T. Schimmel, et.al. , Phys. Rev. Lett. 93, 128303, Sep. 2004.
[7] H.G. Rangaraju, U. Venugopal et.al. , “Low power reversible parallel binary adder/subtractor,” International Journal of VLSI Design & Communication Systems, pp-23-34, arXiv: 1009.6218, 2010.
[8] P. Kaur, B.S. Dhaliwal, “Design of Fault Tolearnt Full Adder/Subtractor Using Reversible Gates,” 2012 International Conference on Computer Communication and Informatics (ICCCI-2012), Coimbatore, Jan. 10 – 12, 2012.
[9] S. Sultana and K. Radecka, “Reversible Adder/Subtractor with Overflow Detector,” IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS), Aug. 2011.
[10] A.K. Biswas et.al, “Efficient approaches for designing reversible Binary Coded Decimal adders,” Microelectronics journal, vol. 39, issue 12, pp.1693-1703, December 2008.
[11] Ri-gui Zhou, Man-qun Zhang, Qian Wu, Yan-Cheng Li, “Optimization Approaches for Designing a Novel 4-Bit Reversible Comparator,” Int. J. of Theoretical Physics, 52, pp. 559-575, 2013.
[12] Md. Saiful Islam and Md. Rafiqul Islam, “Minimization of Reversible Adder Circuits,” Asian Journal of Information Technology, Vol. 4, No. 12, pp. 1146-1151, 2005. Rahman, Saiflil Islam, Zerina Begum, Hafiz, Mahmud, "Synthesis of Fault Tolerant Reversible Logic Circuits", IEEE, 978-1-4244-2587- 7/09,2009.
[13] Kamalika, Gaurav, Wille, "Exploiting Negative Control Lines in the Optimization of Reversible Circuits", Springer- Verlag Berlin Heidelberg 2013.
[14] H. M.H. Babu and AR. Chowdhury. "Design of a compact reversible binary coded decimal adder circuit". Elsevier Jour. of Systems Architecture, 52:272-282, 2006.
[15] Ashis Kumer Biswas, Md. Mahmudul Hasan, Ahsan Raja Chowdhury, and Hafiz Md. Hasan Babu. "Efficient approaches for designing reversible binary coded decimal adders".Microelectron. 1., 39(12): 1693- 1703,2008.
[16] M.K. Thomsen and R.Gruck. "Optimized reversible binary-coded decimal adders". 1. Syst.Archit., 54(7):697-706, 2008.
[17] M. Mohammadi, M. Eshghi, M. Haghparast, and A Bahrololoom."Design and optimizationof reversible bcd adderlsubtractor circuit for quantum and nanotechnology based systems".World Applied Sciences Journal, 4(6):787-792, 2008.
[18] M. Mohammadi, M. Haghparast, M. Eshghi, and K. Navi. "Minimization optimization of reversible bcd-full adderlsubtractor using genetic algorithm and don`t care concept". InternationalJ. Quantum Information, 7(5):969-989, 2009.
[19] Himanshu Thapliyal and Nagarajan Ranganathan, "Design of Efficient Reversible Logic based Binary and BCD adder circuits", ACM Journal on Emerging Technologies in Computing Systems, Vol. 9, Issue 3, September 2013.
[20] H.R. Bhagyalakshmi and M.K. Venkatesha, "Optimized reversible BCD adder using new reversible logic gates", Journal of Computing, Volume 2, Issue 2, February 2010, ISSN 2151-9617.
[21] Hafiz Md. Hasan Babu and Ahsan Raja Chowdhury, "Design of a Reversible Binary Coded Decimal Adder by using Reversible 4-bit Parallel Adder ", Proceedings of the 181h International Conference on VLSI Design and 4th International Conference on Embedded Systems Design, 1063-9667/05, IEEE 2005.
[22] K. V. R. M. Murali, N. Sinha, T. S. Mahesh, M. H. Levitt, K. V. Ramanathan, and A Kumar. "Quantum information processing by nuclear magnetic resonance: experimental implementation of half-adder and subtractor operations using an oriented spin"-7/2 system. Physical Review A, 66(2):022313, 2002.
[23] Kai-Wen Cheng and Chien-Cheng Tseng. "Quantum full adder and subtractor". ElectronicsLetters, 38(22): 1343- 1344, Oct 2002.

Keywords
Reversible logic, DR Gate, Nanotechnology, Optical Computing.