Comparative Analysis of Low Power Adiabatic Logic Circuits in DSM Technology
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International Journal of Engineering Trends and Technology (IJETT) |  |
| © 2017 by IJETT Journal | ||
| Volume-45 Number-3 |
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| Year of Publication : 2017 | ||
| Authors : Shaefali Dixit, Ashish Raghuwanshi |
Citation
Shaefali Dixit, Ashish Raghuwanshi " Comparative Analysis of Low Power Adiabatic Logic Circuits in DSM Technology ", International Journal of Engineering Trends and Technology (IJETT), V45(3),98-102 March 2017. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
Abstract
With the continuous scaling down of technology, in the field of integrated circuit design, low power dissipation has become one of the primary focus of the research. With the increasing demand for low power devices adiabatic logic gates proves to be an effective solution. This paper investigates different adiabatic logic families such as ECRL, 2N-2N2P and PFAL. The main aim of this paper is to simulate various logic gates using conventional CMOS and different adiabatic logic families, and thus compare for the effectiveness in terms of lower power dissipation. All simulations are carried out using HSPICE at 65nm technology with supply voltage is 1V at 100MHz frequency, for fair comparison of results W/L ratio of all the circuit is same. Finally average power dissipation characteristics are plotted with the help of a graph and comparisons are made between different logic families.
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Keywords
Low power, CMOS, Adiabatic logic, ECRL, 2N-2N2P, PFAL, Power dissipation, Four phased power clock.