IJBTT

Implementation of High Performance Vedic Multiplier Based on Efficient carry select adder

	International Journal of Engineering Trends and Technology (IJETT)
	© 2017 by IJETT Journal
	Volume-45 Number-9
	Year of Publication : 2017
	Authors : Anupama.k, Mrs.Lisa.c
	DOI :  10.14445/22315381/IJETT-V45P284

Citation 

Anupama.k, Mrs.Lisa.c "Implementation of High Performance Vedic Multiplier Based on Efficient carry select adder", International Journal of Engineering Trends and Technology (IJETT), V45(9),443-448 March 2017. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

Abstract
In digital system multiplication is one of the most important function. Vedic maths, one of the ancient mathematics system make this tedious task much simple, efficient and suitable for VLSI implementation. This project implements high performance Vedic multiplier based on efficient square root carry select adder (SCSLA).The heart of a multiplier is adder.In this project the improvement is done on the adder to improve the total performance of the multiplier.In the existing system the first stage of SCSLA is RCA(ripple carry adder) with Cin=0 and second stage is BCE-1(Binary to excess one) converter.In moderrn digital systems parallel prefix adders(PPA) have been considered as the most efficient system for binary addition. Here,the first stage of the square root carry select adder is replaced by efficient and most common parallel prefix adders (PPA) such as Kogg stone adder(KSA),Brent-kung adder(BKA) and the hybrid of these two the Han Carlson adder (HCA). A comparative study is carried out to find out the efficient vedic multiplier with parallel prefix adder based SCLA .The result analysis shows that Vedic multiplier with HCA based squre root carry select adder exhibits efficient performance.The system is coded in Verilog HDL(hardware description language)and simulation,synthesis is carried out by using Model Sim 6.4a,Xilinx 14.5i.The implementation is done on Xilinx Spartan 3E FPGA(field programmable gate array).

 References

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Keywords
Brent-kung adder(BKA),Han-carlson adder(HCA),Kogg-stone adder(KSA), Parallel prefix adder(PPA), Ripple carry adder(RCA),Square root carry select adder(SCSLA), Vedic multiplier.