Dynamically Reconfigurable RISC Microprocessor design using MIPS Instruction Set

Dynamically Reconfigurable RISC Microprocessor design using MIPS Instruction Set

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2017 by IJETT Journal
Volume-47 Number-5
Year of Publication : 2017
Authors : Neethu K Krishnan, Bhavya Das D
DOI :  10.14445/22315381/IJETT-V47P246

Citation 

Neethu K Krishnan, Bhavya Das D "Dynamically Reconfigurable RISC Microprocessor design using MIPS Instruction Set", International Journal of Engineering Trends and Technology (IJETT), V47(5),287-289 May 2017. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

Abstract
Today’s world suggests multifunction in each products. This paper design a RISC processor using MIPS instruction set architecture which supports multifunctioning. Dynamic Reconfiguration refers to the ability of the Processor to update its internal Instruction Decode and Execute stage in order to support new functions, while the system is running. This project presents a principle on how performance can be improved in the context of microprocessor Units applications, using the MIPS instruction set.

 References

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Keywords
RISC, MIPS, dynamically reconfigurable.