Design of Low Power One Bit Hybrid CMOS Full Adder Cells

Design of Low Power One - Bit Hybrid - CMOS Full Adder Cells

  ijett-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2013 by IJETT Journal
Volume-4 Issue-5                      
Year of Publication : 2013
Authors : Sushil B. Bhaisare , Sonalee P. Suryawanshi , Sagar P. Soitkar

Citation 

Sushil B. Bhaisare , Sonalee P. Suryawanshi , Sagar P. Soitkar. "Design of Low Power One - Bit Hybrid - CMOS Full Adder Cells". International Journal of Engineering Trends and Technology (IJETT). V4(5):1810-1814 May 2013. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group.

Abstract

The aim of our work is to evaluate the pe rformance of One - bit Hybrid full adder cell. To achieve a good - drivability, noise - robustness, and low energy operations f or deep - sub micrometer, we explore Hybrid - CMOS style design. Hybrid - CMOS design styles utilize various CMOS logic style circuit to build new Full Adder with desired performance. This Full Adder is categorized into three modules. We compared the proposed Fu ll Adder cell with conventional static CMOS logic styles Adder Cells like C - CMOS, CPL, TFA, TGA and with some hybrid cells at different Load condition. Each Cell showed different power consumption, Delay, PDP and driving capability. The circuits being stud ied are optimized for energy efficiency at 0.18um CMOS process Technology.

References

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Keywords
Full Adders, Hybrid CMOS Design style, deep - sub micrometer technology, low power, Delay & PDP