Floating Point Engine using VHDL

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2014 by IJETT Journal
Volume-8 Number-4                          
Year of Publication : 2014
Authors :  Najib Ghatte , Shilpa Patil , Deepak Bhoir
  10.14445/22315381/IJETT-V8P236

MLA 

Najib Ghatte , Shilpa Patil , Deepak Bhoir."Floating Point Engine using VHDL", International Journal of Engineering Trends and Technology(IJETT), V8(4),198-203 February 2014. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

Abstract

Floating Point arithmetic is by far the most used way of approximating real number arithmetic for performing numerical calculations on modern computers. Each computer had a different arithmetic for long time: bases, significant and exponents’ sizes, formats, etc. Each company implemented its own model and it hindered the portability between different equipments until IEEE 754 standard appeared defining a single and universal standard. This paper deals with the implementation of single precision as well as double precision floating point arithmetic adder as well as multiplier according with the IEEE 754 standard and using the hardware programming language VHDL. VHDL Codes so designed are simulated for various set of inputs and desired results are obtained. Codes are synthesized on device XC3S5000 having package as FG900 of Spartan®-3 FPGA family.

References

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Keywords
Single precision, double precision, FPGA, Spartan, IEEE-754, Floating-point arithmetic, VHDL, Xilinx