Floating Point Engine using VHDL

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
© 2014 by IJETT Journal
Volume-8 Number-4                          
Year of Publication : 2014
Authors :  Najib Ghatte , Shilpa Patil , Deepak Bhoir


Najib Ghatte , Shilpa Patil , Deepak Bhoir."Floating Point Engine using VHDL", International Journal of Engineering Trends and Technology(IJETT), V8(4),198-203 February 2014. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group


Floating Point arithmetic is by far the most used way of approximating real number arithmetic for performing numerical calculations on modern computers. Each computer had a different arithmetic for long time: bases, significant and exponents’ sizes, formats, etc. Each company implemented its own model and it hindered the portability between different equipments until IEEE 754 standard appeared defining a single and universal standard. This paper deals with the implementation of single precision as well as double precision floating point arithmetic adder as well as multiplier according with the IEEE 754 standard and using the hardware programming language VHDL. VHDL Codes so designed are simulated for various set of inputs and desired results are obtained. Codes are synthesized on device XC3S5000 having package as FG900 of Spartan®-3 FPGA family.


[1] William R. Dieter, Akil Kaveti, Henry G. Dietz, “Low-Cost Microarchitectural Support for Improved Floating-Point Accuracy”, March 2007.
[2] Pat Kusbel, “Control and Computing System for the Compact Microwave Radiometer for Humidity Profiling” B.Tech thesis, Department of Electrical and Computer Engineering, Colorado State University, March 2006.
[3] Alex N. D. Zamfirescu, “Floating Point Type for Synthesis”, CA USA, 2000. [4] John J. G. Savard (2012) Floating-Point Formats [Online]. Available: http://www.quadibloc.com/comp/cp0201.htm
[5] Steve Hollasch, (2005) IEEE Standard 754 Floating Point Numbers [Online]. Available: http://steve.hollasch.net/cgindex/coding/ieeefloat.html
[6] Sun Microsystems, “Numerical Computation Guide”, Ch. 4 Exception and Exception Handling.
[7] Nathan Whitehead, Alex Fit-Florea, “Precision & Performance: Floating Point and IEEE 754 Compliance for NVIDIA GPUs”, 2011
[8] Arturo Barrabés Castillo, “Design of single precision Float Adder (32-Bit Numbers) according to IEEE 754 Standard using VHDL” M.Tech, thesis, Slovenská Technical University, Apr. 2012
[9] Spartan-3 FPGA Family, Xilinx, 2013.
[10] R. Sai Siva Teja, A. Madhusudhan, “FPGA Implementation of Low-Area Floating Point Multiplier Using Vedic Mathematics” in International Journal of Emerging Technology and Advanced Engineering, Dec 2013.

Single precision, double precision, FPGA, Spartan, IEEE-754, Floating-point arithmetic, VHDL, Xilinx