Volume-20 Number-6 February 2015

S.No
Title/Author Name
Ref. No
51

Study on Dual Watermarking

- Mrs.S.S.Athalye , Mr. Pranav Gurav , Mr. Rohan Chavan , Mr. Rohit Pashte Hajare

       

IJETT-V20P251
52

Design of Low Power L1 Cache Using CBF Based TOB Architecture in Embedded Processors

- Mrs.S.Brindha, Ms.B.Kavitha

       

IJETT-V20P252
53

Recursive CORDIC- Based Low Power DCT Architecture

- Mrs. M.Nidhiya Aravind, Ms.A.Shanmukapriya

       

IJETT-V20P253
54

Area optimized in storage area network using Novel Mix column Transformation in Masked AES

- Mrs.S.Anitha, Ms.M.Suganya

       

IJETT-V20P254
55

A Design of Low Power NAND based Multiplexer Circuit in CMOS to DPL Converter for Smart card Security System

- Ms.S.Nagalakshmi, Ms.R.Chitra

       

IJETT-V20P255