Implementation and Optimization of 4×4 Luminance Intra Prediction Modes on FPGA

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2014 by IJETT Journal
Volume-10 Number-1
Year of Publication : 2014
Authors : Ashwini.V , Madhusudhan.K.N
  10.14445/22315381/IJETT-V10P210

MLA 

Ashwini.V , Madhusudhan.K.N. "Implementation and Optimization of 4×4 Luminance Intra Prediction Modes on FPGA", International Journal of Engineering Trends and Technology (IJETT), V10(1),50-57 April 2014. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

Abstract

This paper proposes an efficient, fast and parallel processing of 4×4 luminance intra prediction implemented on FPGA. H.264[1] advanced video coding is a present generation video compression algorithm which can achieve high compression ratio without degrading the video quality. To achieve high compression H.264 uses various algorithms. Intra prediction [2,3] is one such algorithm to exploit the spatial redundancy in video frames. As we know there is a high correlation between pixels in a video frame. Intra prediction eliminates the correlation between pixels in a same frame to achieve compression. In this paper, luminance part of the image or video frame is taken and intra prediction algorithm is applied. In H.264[1] the luminance part of a video frame is divided into 4×4 or 16×16 block size depending on user application on image quality. Here we use 4×4 block size intra prediction. This has nine modes [1,2,3] to predict an image using reconstructed neighbor pixels of adjacent blocks. Processing of nine modes of 4×4 luminance intra prediction requires huge computations and has high latency. So we propose a method to reduce computations and processing all modes in parallel to achieve lower latency. This project is designed in Verilog using Xilinx ISE, simulated using Xilinx ISIM, synthesized and implemented on Virtex-6(Device: xc6vcx130T, Package: ff484, Speed:-2) FPGA. Project is implemented on FPGA’s because present generation FPGA’s are very much faster and has more resources and design time and time to market is less compared to ASIC’s. The design is synthesized using Xilinx XST and power consumption is calculated using XPower Analyzer. Results achieved is analyzed and compared to check the design works perfectly. This project is very useful for video application which needs faster processing and can be used as intra prediction IP (Intellectual Property).

References

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Keywords
H.264, Luminance, 4×4, Intra Predictions, mode.