Area Efficient Carry Select Adder (AE-CSLA) using Cadence Tools

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
© 2014 by IJETT Journal
Volume-10 Number-10
Year of Publication : 2014
Authors : Gagandeep Singh , Chakshu Goel


Gagandeep Singh , Chakshu Goel. "Area Efficient Carry Select Adder (AE-CSLA) using Cadence Tools", International Journal of Engineering Trends and Technology (IJETT), V10(10),492-495 April 2014. ISSN:2231-5381. published by seventh sense research group


To perform fast addition operation, CSLA is one of the fastest adders used in many data-processing processors. Analyzing the structure of Regular CSLA (R-CSLA) and Modified CSLA (M-CSLA), there is a scope to reduce the area further. This work uses a simple gate level modification and a modified XOR gate is proposed to be used in the circuit. Based on this modification, 16-bit Area Efficient CSLA (AE-CSLA) is designed which provides 32% reduction in area when compared with R-CSLA and 12.5% reduction in area when compared with M-CSLA. This work is implemented in CADENCE VIRTUOSO using 180nm CMOS process technology.


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Binary to Excess-1 converter (BEC), Carry Select Adder(CSLA), Multiplexer(MUX), Ripple Carry Adder(RCA), Exclusive OR(XOR).