Comparative Analysis of 1Bit Adiabatic Full Subtractor Designed in 45nm Technology

Comparative Analysis of 1-Bit Adiabatic Full Subtractor Designed in 45nm Technology

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2014 by IJETT Journal
Volume-10 Number-11
Year of Publication : 2014
Authors : Nikhil Deo , Rusni Kima Mangang
  10.14445/22315381/IJETT-V10P307

Citation 

Nikhil Deo , Rusni Kima Mangang. "Comparative Analysis of 1-Bit Adiabatic Full Subtractor Designed in 45nm Technology", International Journal of Engineering Trends and Technology (IJETT), V10(11),541-544 April 2014. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

Abstract

This paper presents a comparative analysis of a 1-bit adiabatic full subtractor designed in 45nm technology node. Adiabatic logic is a low power digital circuit design technique which is much more power efficient than CMOS logic. We designed 1-bit full subtractor using 2N2N2P and DCPAL adiabatic logic styles which are two of the popular adiabatic logic styles. We found that the full subtractor designed using DCPAL saves much more power than 2N2N2P adiabatic logic style, also we simulated our circuits at two different frequencies of 100MHz and 300MHz.

References

[1] Y. Moon, and D.-K. Jeong, “An Efficient charge recovery logic circuit,” IEEE J. of Solid-State Circuits, vol. 31, no. 4, pp. 514–522, 1996.
[2] A. Kramer, J.S. Denker, B. Flower, and J. Moroney, “2nd order adiabatic computation with 2N-2P and 2N-2N2P logic circuits,” Int. Symp. Low Power Design, pp. 191-196, 1995.
[3] A. Vetuli, S.D. Pascoli, and L. M. Reyneri, “Positive feedback in adiabatic logic,” Electronics Letters, vol. 32, no. 20, pp. 1867–1869, 1996.
[4] V. S. Kanchana Bhaaskaran and J. P. raina, “Differential Cascode Adiabatic Logic Structure for Low Power”, Jl. of Low Power Electronics, Vol.4, No. 2. Aug. (2008), pp.178-191.
[5] Anantha P. Chandrakasan, R.W. Brodersen, “Low Power Digital CMOS Design”, Kulwer Academic Publisher, p.55.
[6] J.G. Koller and W.C. Athas, “Adiabatic switching, low energy computing, and the physics of storing and erasing information,” In proc. of PhysCmp’92, IEEE Press, pp. 267-270, 1993.
[7] Philip Teichmann, “Adiabatic Logic Future Trend and System Level Perspective”, pp. 131-132, Springer Series in Advanced Microelectronics,2012.

Keywords
Adiabatic logic, 2N2N2P, DCPAL, low power