A Full swing Ex-OR/Ex-NOR Gate Circuit Using Pass Transistor Logic with Five Transistors

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
© 2014 by IJETT Journal
Volume-11 Number-6
Year of Publication : 2014
Authors : Mrudula Singamsetti , Sarada Musala


Mrudula Singamsetti , Sarada Musala . "A Full swing Ex-OR/Ex-NOR Gate Circuit Using Pass Transistor Logic with Five Transistors", International Journal of Engineering Trends and Technology (IJETT), V11(6),277-283 May 2014. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group


The Ex-OR/Ex-NOR gates are the basic building blocks of various digital system applications like adder, comparator, and parity generator/checker and encryption processor. This paper proposes a 5T full swing pass transistor based Ex-OR/Ex-NOR circuit using new 3T full swing pass transistor Ex-OR gate. The new Ex-OR with three transistors is proposed by modifying the existed 3T cross coupled Ex-OR gate to get full output voltage swing. Then one bit full adder, 4-bit ripple carry adder and 8-bit ripple carry adder are constructed with use of the proposed 5T full swing Ex-OR/Ex-NOR circuit. All the proposed and existing circuits are simulated and compared with Cadence Spectre 180nm CMOS technology with the supply voltage of 0.6V to1.8V. The simulation results show that the proposed circuits achieve a full output voltage swing for all the input combinations with high speed. And the proposed full adder and ripple carry adder circuits have better Power Delay Product than the existing circuits.


[1] D. Radhakrishanan, “Low-voltage low power CMOS full adder”, in Proc. IEE Circuits Devices Syst ., vol. 148, no. 1, p. 19–24, Feb.2001.
[2] M. A. Elgamel, S. Goel, and M. A. Bayoumi, “Noise tolerant low voltage XOR-XNOR for fast arithmetic ,” in Proc. Great Lake Sym. VLSI, Washington DC, April. 28-29, 2003, pp. 285-288.
[3] Rajeev Kumar and Vimal Kant Pandey, “A New 5-Transistor XOR-XNOR circuit based on the pass transistor logic,” in Proc IEEE World Congress on Information and Communication Technologies, 2011.
[4] Venkata Rao Tirumalasetty. and Srinivasulu. Avireni., “Modified level restorers using current sink and current source inverter structures for B B L-PT Full adder,” in Proc. Radio Engineering., vol. 21, December. 2012.
[5] R. Zimmermann, W. Fichtner, “Low power logic styles CMOS versus pass-transistor logic,” in Proc IEEE Journal solid state circuits.,vol. 32,pp. 1079-1090, 1997.
[6] Issam. S, KHATER. A, Bellaouar. A, Elmasry. M. I, “Circuit techniques for CMOS low power high performance multipliers,” IEEE Journal solid state circuits, vol. 31, 1996.
[7] I. Hassoune, Flandre. D, Oconnor. I, Legat. J.D. “A new efficient design of a power-aware full adder,” IEEE Transactions on Circuits and Systems-I, Regular papers, vol. 57, no. 8, p. 2066-2074, 2010.
[8] Weste Neil., Eshraghian Kamaran, Principles of CMOS VLSI Design, A System Perspectives., Addison-Wesley, 1988.
[9] V.V.Shubin, “New CMOS circuit implementation of a one- bit full adder cell,” Russian Microelectronics Journal, vol. 40, no. 2, p. 130-139, 2011.

Propagation Delay, Power Dissipation, Output voltage swing, PDP, Ex-OR/Ex-NOR, Full adder, Ripple carry adder.