Upgrading the Performance of VLSI Circuits using FinFETs
|International Journal of Engineering Trends and Technology (IJETT)||
|© 2014 by IJETT Journal|
|Year of Publication : 2014|
|Authors : Tushar Surwadkar , Swapnali Makdey , Deepak Bhoir
Tushar Surwadkar , Swapnali Makdey , Deepak Bhoir. "Upgrading the Performance of VLSI Circuits using FinFETs", International Journal of Engineering Trends and Technology (IJETT), V14(4),179-184 Aug 2014. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
In the world of integrated circuits, CMOS has lost it’s credentialed during scaling beyond 32nm. The main drawback of using CMOS transistors are high power consumption and high leakage current. Scaling causes severe Short Channel Effects (SCE) which are difficult to suppress. As technology is scaled down, the importance of leakage current and power analysis for VLSI design is increasing since Short-channel effects cause an exponential increase in the leakage current and power dissipation. Multi-gate MOSFET technologies mitigate these limitations by providing a stronger control over a thin silicon body with multiple electrically coupled gates. Enormous progress has been made to scale transistors to even smaller dimensions to obtain fast switching transistors, as well as to reduce the power consumption. Even though the device characteristics are improved, high active leakage remain a problem. FinFET has become the most promising substitute to bulk CMOS technology because of reducing short channel effect and the similarity of the fabrication steps to the existing standard CMOS technology. FinFET device has a higher controllability, resulting relatively high lon/loff ratio. FinFET devices can be used to increase the performance by reducing the leakage current and power dissipation, because front and back gates both can be controlled.(independently or both simultaneously). In this paper, Dual-gate FinFET with shorted gates of either side is used for better performance to reduce the leakage and hence power consumption. In this work, the basic gates, combinational circuit and are modelled in HSPICE software using CMOS structures and FinFET structure are analysed and their performances like power consumption and speed are compared. Latch based on tied-gate FinFETs is proposed in this paper to simultaneously reduce the power consumption and the circuit area.
 J. Colinge, “FinFETs and Other Multi-Gate Transistors”. New York: Springer-Verlag, 2008.
 Avant Star Hspice Manual Release 1 998.2 July 1998. Copyright ã 1998 Avant! Corporation and Avant!
 Hspice Tutorial from University of California at Berkeley. College of Engineering Department of Electrical Engineering and Computer Sciences
 Digital Design Textbook by M.Morris Mano-Applied Electronics Engineering
 Modern Digital Electronics Textbook by Jain. Tata McGraw-Hill Education, Jun 1, 2003
 Nirmal, Vijaya Kumar, Sam Jabaraj “Nand Gate Using Finfet For Nanoscale Technology”. Nirmal et al. / International Journal of Engineering Science and Technology Vol. 2(5), 2010, 1351-1358
 Aditya Dayal,” “A novel double gate FinFET Transistor: Device Design and Analysis” presentation.
 ] E. J. Frank, R. H. Dennard, E. Nowak, P. M. Solomon, Y. Taur, and H.-S. P. Wong. “Device scaling limits of Si MOSFETs and their application dependencies”. Proc. IEEE, 89(3):259–288, (2001).
 T.-J. King, “FinFETs for nano scale CMOS digital integrated circuits”. In Proc. Int. Conf. Computer-Aided Design, pages 207–210, (2005).
 ] L. Wei, Z. Chen, and K. Roy, “Double gate dynamic threshold voltage (DGDT) SOI MOSFETs for low power high performance designs.” In Proc. IEEE Int. SOI Conf., pages 82–83, (1997).
 I. Yang, A. Chandrakasan, and D. Antoniadis. “Back gated CMOS on SOIAS for dynamic threshold voltage control”. IEEE Trans. Electron Devices, 44(5):822–831, (1997).
 Etienne Sicard, Sonia Delmas, “Basics of CMOS cell design” book, (2006).
 ] Anish Muttreja, Niket Agarwal and Niraj K. Jha, “CMOS logic design with independent-gate FinFETs” ©2007IEEE
 ] I. Aller “The double-gate FinFET: Device impact on circuit design.” In Proc. Int. Solid-State Circuits Conf., pages 14–15 (and visual supplements, pp. 655–657), (2003).
 Niraj K. Jha, Anish Muttreja and Prateek Mishra “Low-power FinFET Circuit Design”presentation.
 Sriramkumar Venugopalan, Muhammed A. Karim, Ali M. Niknejad and Chenming Hu “Compact Models for Real Device Effects in FinFETs ” (Quantum-Mechanical confinement and Double junctions in FinFETs) SISPAD 2012, September 5-7, 2012, Denver, CO, USA FLEXChip Signal Processor (MC68175/D), Motorola, 1996.
“BSIM-CMG106.0.0 Technical Manual” & “BSIM4.7.0 Technical Manual”
 Das, K.K. ; Joshi, R.V. ; Ching-Te Chuang “Leakage power analysis of 25-nm double-gate CMOS devices & circuits”
 X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski,E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J.King, J. Bokor, and C. Hu, “Sub-50 nm FinFET: PMOS,” in IEDMTech.Dig.1999, pp.67–70.
 Dong-Soo Woo, Jong-Ho Lee, Woo Young Choi, Byung-Yong Choi, Young-Jin Choi, Jong Duk Lee, Member, IEEE,and Byung-Gook Park, Member, IEEE” “Electrical Characteristics of FinFET With Vertically Nonuniform Source/Drain Doping Profile” ieee transactions on nanotechnology, vol. 1, no. 4, december2002
 Bing-Yue Tsui, Senior Member, IEEE, and Chia-Pin Lin, Student Member, IEEE “A Novel 25-nm Modified Schottky-Barrier FinFET with High Performance” ieee electron device letters, vol. 25, no. 6, june 2004
Short channel effects, FinFET, tied gate