Upgrading the Performance of VLSI Circuits using FinFETs

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
© 2014 by IJETT Journal
Volume-14 Number-4
Year of Publication : 2014
Authors : Tushar Surwadkar , Swapnali Makdey , Deepak Bhoir


Tushar Surwadkar , Swapnali Makdey , Deepak Bhoir. "Upgrading the Performance of VLSI Circuits using FinFETs", International Journal of Engineering Trends and Technology (IJETT), V14(4),179-184 Aug 2014. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group


In the world of integrated circuits, CMOS has lost it’s credentialed during scaling beyond 32nm. The main drawback of using CMOS transistors are high power consumption and high leakage current. Scaling causes severe Short Channel Effects (SCE) which are difficult to suppress. As technology is scaled down, the importance of leakage current and power analysis for VLSI design is increasing since Short-channel effects cause an exponential increase in the leakage current and power dissipation. Multi-gate MOSFET technologies mitigate these limitations by providing a stronger control over a thin silicon body with multiple electrically coupled gates. Enormous progress has been made to scale transistors to even smaller dimensions to obtain fast switching transistors, as well as to reduce the power consumption. Even though the device characteristics are improved, high active leakage remain a problem. FinFET has become the most promising substitute to bulk CMOS technology because of reducing short channel effect and the similarity of the fabrication steps to the existing standard CMOS technology. FinFET device has a higher controllability, resulting relatively high lon/loff ratio. FinFET devices can be used to increase the performance by reducing the leakage current and power dissipation, because front and back gates both can be controlled.(independently or both simultaneously). In this paper, Dual-gate FinFET with shorted gates of either side is used for better performance to reduce the leakage and hence power consumption. In this work, the basic gates, combinational circuit and are modelled in HSPICE software using CMOS structures and FinFET structure are analysed and their performances like power consumption and speed are compared. Latch based on tied-gate FinFETs is proposed in this paper to simultaneously reduce the power consumption and the circuit area.


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Short channel effects, FinFET, tied gate