Implementation of High Throughput FFT for Communication

Implementation of High Throughput FFT for Communication

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2014 by IJETT Journal
Volume-14 Number-6
Year of Publication : 2014
Authors : Leenu Mathew Thomas , R.Ramya
  10.14445/22315381/IJETT-V14P252

Citation 

Leenu Mathew Thomas , R.Ramya. "Implementation of High Throughput FFT for Communication", International Journal of Engineering Trends and Technology (IJETT), V14(6),267-270 Aug 2014. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

Abstract

Most of the wireless standards utilize OFDM technique to enhance the transmission rate which is the vital requirement that is to be met today. The increases in the throughput of FFT block in OFDM system which in turn improves the transmission rate of the system. This paper presents high throughput FFT processor based on Multi-path delay feedback architecture for OFDM systems. Mixed Radix-2/22/23/24 DIF FFT algorithm is used. A comparison is done for different pipeline architecture such as MDF, MDC and SDF using the same algorithm with respect to throughput. The design is fully coded in VHDL, simulated in Xilinx ISE 13.2 and is implemented on Virtex-5 FPGA.

Reference

[1] Shousheng He and Mats Torkelson, “Designing Pipeline FFT Processor for OFDM (de)Modulation”, IEEE International Symposium on Signals, Systems, and Electronics, pp.257– 262, 1998.
[2] C. Fan, M. Lee, G. Su, “Efficient low multiplier cost 256-point FFT design with radix 24 SDF architecture”, IEEE Asia Pacific Conference on Circuits and Systems, pp.1935–1938, 2006.
[3] M.J.S Rangachar, “VLSI Implementation and Performance Analysis of Efficient Mixed-radix 8-2 FFT Algorithm with Bit Reversal for the Output Sequences”, Journal of Theoretical and Applied Information Technology 2010.
[4] C.Vennila, G.Lakshminarayanan, Seok-Bum Ko, “Dynamic Partial Reconfigurable FFT for OFDM based Communication Systems”, Springer Circuit System Signal processing, p 1-18, October 2011.
[5] Y.-N. Chang, "An efficient VLSI architecture for normal I/O order pipeline FFT design", IEEE Trans. Circuits Syst. II, Exp. Briefs, Vol. 55, No. 12, pp. 1234-1238, Dec. 2008.
[6] Yang K.J, and Chuang G.C.H, “A MDC FFT Processor with Variable Length for MIMO-OFDM”, IEEE Transactions on VLSI systems, Vol. 21, pp.720-731, 2013.

Keywords

OFDM, FFT, FPGA