A Low Power VLSI Design of an All Digital Phase Locked Loop

A Low Power VLSI Design of an All Digital Phase Locked Loop

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)
  
© 2014 by IJETT Journal
Volume-16 Number-6 
Year of Publication : 2014
Authors : Nakkina Vydehi , A. S. Srinivasa Rao
  10.14445/22315381/IJETT-V16P256

Citation 

Nakkina Vydehi , A. S. Srinivasa Rao. "A Low Power VLSI Design of an All Digital Phase Locked Loop", International Journal of Engineering Trends and Technology (IJETT), V16(6),288-292 Oct 2014. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

Abstract

Phase locked loop is a familiar circuit for high frequency application and very short interlocking time. In this paper we have implemented and analysed All Digital Phase locked loop (ADPLL), as the present applications requires a low cost , low power and high speed Phase locked loops. The design is synthesized in Xilinx ISE software. This work Implements an ADPLL with Nyquist rate phase detector which is basically a digital multiplier, simulation results proves a very high speed of operation for low frequency ranges and resource utilization on FPGA proves the structure simpler.

References

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Keywords
ADPLL, DCO, FPGA, Loop Filter, Phase Detector, PLL, wireless communications, Xilinx