Reduction of Ground Bounce Noise in 14T Full Adder by Using Various Power Gating Techniques
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International Journal of Engineering Trends and Technology (IJETT) |  |
| © 2014 by IJETT Journal | ||
| Volume-17 Number-1 |
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| Year of Publication : 2014 | ||
| Authors : P.Balasubramanyam , D. Sreekanth Reddy |
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 10.14445/22315381/IJETT-V17P202 |
Citation
P.Balasubramanyam , D. Sreekanth Reddy . "Reduction of Ground Bounce Noise in 14T Full Adder by Using Various Power Gating Techniques", International Journal of Engineering Trends and Technology (IJETT), V17(1),9-13 Nov 2014. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
Abstract
The main objective is to compare the existing full adders circuits and their performances to design a Low Power Full Adder having improved result as compared to existing Full Adders. The Full Adder circuit is a very important part in application like Digital Signal process (DSP) design, chip, and microcontroller and processing units. This paper discusses the evolution of full adder circuits in terms of lesser power consumption higher speed. As low power circuits are most popular now a days as the scaling increase the leakage powers in the circuit also increases rapidly so for removing these kind of leakages and to provide a better power efficiency we are using many types of power gating techniques. In this paper we are going to analyse the static power dissipation on 14TFull Adder using different types of power gated circuits using low power VLSI design techniques and we are going to display the comparison results in TSMC018 Nanometre Technology. The simulations were done using Tanner Tools and the results were given below.
References
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Keywords
Power Gating, Static Power, Tanner Tool