FPGA Implementation of Viterbi Decoder using Trace back Architecture
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International Journal of Engineering Trends and Technology (IJETT) |  |
| © 2011 by IJETT Journal | ||
| Volume-1 Issue-1 |
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| Year of Publication : 2011 | ||
| Authors :Swati Gupta, Rajesh Mehra | ||
Citation
Swati Gupta, Rajesh Mehra. "FPGA Implementation of Viterbi Decoder using Trace back Architecture". International Journal of Engineering Trends and Technology (IJETT),V1(1):131-134 May to June 2011. ISSN:2231-5381. www.ijettjournal.org. Published by Seventh Sense Research Group.
Abstract
Error correction is an integral part of any communication system and for this purpose, the convolution codes are widely used as forward error correction codes. For decoding of con volution codes, at the receiver end Viterbi Decoder is being employed. The parameters of Viterbi algorithm can be changed to suit a specific application. The high speed and small area are two important design parameters in today’s wireless technology . I n t his paper, a high speed feed forward viterbi decod er has been designed using track back architecture and embedded BRAM of target FPGA . The proposed viterbi decoder has been designed wit h Matlab, simulated with Xilinx DSP Tool , synthesized with Xilinx Synth esis Tool (XST ), and implemented on Xilinx Spartan 3E based xc3s500e FPGA device. The results show that the proposed design can operate at an estimated frequency of 8 6.6 MHz by consuming considerably less resources on target device to provide cost effectiv e solution for wireless applications.
References
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Keywords
DSP, FPGA, Matlab, Viterbi Decoder , XST