A High Resolution All Digital Duty Cycle Corrector Using Reversible Multiplexer Logic

A High Resolution All Digital Duty Cycle Corrector Using Reversible Multiplexer Logic

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2015 by IJETT Journal
Volume-22 Number-1
Year of Publication : 2015
Authors : Mrs. KIRUTHIKA.S.V, Dr. (Mrs.) R. SUDARMANI
DOI :  10.14445/22315381/IJETT-V22P207

Citation 

Mrs. KIRUTHIKA.S.V, Dr. (Mrs.) R. SUDARMANI"A High Resolution All Digital Duty Cycle Corrector Using Reversible Multiplexer Logic", International Journal of Engineering Trends and Technology (IJETT), V22(1),27-30 April 2015. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

Abstract

In low power design and high speed applications, a high resolution all digital duty cycle corrector (HR-ADDCC) is proposed. It is used to correct the duty cycle error and to achieve an exact 50% output duty cycle. A reversible multiplexer logic is used to obtain a glitch free circuit, which is more feasible compared to conventional logic gates. In addition, a reversible multiplexer based DCC (Duty Cycle Corrector) is proposed to achieve an exact 50% output duty cycle with low power area and high resolution duty cycle correction. It is suitable for wide operating frequency range in nanometer CMOS technology process.

References

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Keywords
Duty Cycle Corrector (DCC), Delay Locked Loop (DLL), All-Digital Duty Cycle Corrector (ADDCC),Digitally Controlled Delay Line (DCDL).