Low Power Layout Design of Priority Encoder Using 65nm Technology

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
© 2015 by IJETT Journal
Volume-23 Number-9
Year of Publication : 2015
Authors : Amritesh Ojha, Rajesh Mehra


Amritesh Ojha, Rajesh Mehra"Low Power Layout Design of Priority Encoder Using 65nm Technology", International Journal of Engineering Trends and Technology (IJETT), V23(9),450-453 May 2015. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

this paper provides comparative performance analysis of power and area of 4 bit priority encoder using 65nm technology. Two priority encoder approaches are presented, one with semi custom and the other with full custom. The main objective is to compare semi custom and full custom designed layout on the basis of two parameters which is power and area. Both the semi custom circuit simulation and full custom has been done by manually layout created. Creation of layout in both types of method is done at 65nm CMOS technology. The simulation results show that priority encoder using full custom design has improved power efficiency by 0.86 μW and effective area by 12.40 μm2.


[1] Saleh Abdel-hafeez and Shadi Harb, “A VLSI High-Performance Priority Encoder Using Standard CMOS Library”, IEEE Transactions on Circuits and Systems—II: Express Briefs, Vol. 53, No. 8, pp. 597- 601, 2006
[2] Swati Sharma, Rajesh Mehra, “Area & Power Efficient Design of XNOR-XOR Logic Using 65nm Technology”, International Journal of Engineering and Technical Research, pp.57-60, 2014
[3] Sushil B. Bhaisare, Sonalee P. Suryawanshi, Sagar P. Soitkar: Design of Low Power One Bit Hybrid CMOS Full Adder Cells”A New Efficient Design of A Power Aware Full Adder”, IJETT- Volume 4, Issue5-,pp, 1810 -1814, 2013
[4] Min Pan and Chris chu “IPR: An Integrated Placement and Routing Algorithm” Design and Automation Conference 2007, June 4-8, 2007, San Diego, California, USA
[5] José G. Delgado-Frias, and Jabulani Nyathi, “A High-Performance Encoder with Priority Lookahead”, IEEE Transactions on Circuits and Systems—I: Fundamental Theory and Applications, Vol. 47, No. 9, pp.1390-1393, 2000
[6] Pushpa Saini, Rajesh Mehra, “A Novel Technique for Glitch and Leakage Power Reduction in CMOS VLSI Circuits”, International Journal of Advanced Computer Science and Applications, Vol. 3, No. 10,pp.161-168 2013
[7] Cheong KUN, Shaolei Quan, and Andrew Mason, “A Power- Optimized 64-Bit Priority Encoder Utilizing Parallel Priority Look- Ahead”, International Journal of Ad hoc, Sensor & Ubiquitous Computing (IJASUC), Vol.1, no.3, pp.85-91, 2010
[8] Etienne SICARD, Syed Mahfuzul Aziz:“Introducing 65nm technology in Microwind3”, Microwind application Notes, pp. 3, 2006
[9] Vandana Choudhary, Rajesh Mehra:“2- Bit Comparator Using Different Logic Style of Full Adder”, International Journal of Soft Computing and Engineering (IJSCE), Volume-3, Issue-2,pp. 277- 279,2013
[10] M. Morris Mano, Michael D. Ciletti:“Digital Design”, Pearson Education Inc., pp. 167-168, Fourth Edition, 2008
[11] Etienne SICARD: User’s Manual: Microwind and DSCH”, Version 3,pp. 7, 2006
[12] I. Hassoune, D. Flandre, I. O’Connor and J.D.Legat: ULPFA: A New Efficient Design of A Power Aware Full Adder”, IEEE Transactions on Circuits and Systems I-5438,pp.2066-2074, 2008

Priority Encoder, Low power, CMOS, 65nm.