Comparator Design Analysis using Efficient Low Power Full Adder

Comparator Design Analysis using Efficient Low Power Full Adder

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2015 by IJETT Journal
Volume-26 Number-1
Year of Publication : 2015
Authors : Meena Aggarwal, Rajesh Mehra
DOI :  10.14445/22315381/IJETT-V26P210

Citation 

Meena Aggarwal, Rajesh Mehra"Comparator Design Analysis using Efficient Low Power Full Adder", International Journal of Engineering Trends and Technology (IJETT), V26(1),50-54 August 2015. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

Abstract
In today’s electronic industry, low power has emerged as principle theme. This reduction in power consumption and also in form of area, it makes the devices more reliable and efficient. So, CMOS technology has been developed which become best known for low power consumption and miniaturization in chip sizes. In a large-scale digital systems design, Comparator is a eminent to be the useful unit of digital systems and signal processors. In this paper , 32-bit comparator has been designed.. The above said designs are prepared by combining two different design approaches: Gate Diffusion Input (GDI) and PTL. These two techniques are hybridized in a way such that it takes the advantage of both the approaches in order to obtain the good quality performance of the circuit. The performance of this proposed 32-bit comparator by hybridizing the two design styles has been compared in terms of transistor count and power and also shows the effect of voltage variations on the power consumed by the circuit. The transistor level schematic are designed and simulated for its behavior using DSCH-3.1.The layout of simulated circuits are created using Verilog based netlist file which is then simulated in Microwind 3.1 to analyze the performance of comparators at 180 nm CMOS technology. The results shows that with the decrease in voltage, the power consumption also decreases but low voltage level results in increase delay.

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Keywords
ALU, Full Adder , Comparators, CMOS style, Digital Arithmetic, Full, GDI technique, Hybrid, PTL logic, Power Efficient.