Pragmatic Analysis of CNT Interconnects for Nanometer Regime

Pragmatic Analysis of CNT Interconnects for Nanometer Regime

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2015 by IJETT Journal
Volume-28 Number-9
Year of Publication : 2015
Authors : Shailendra Mishra, Divya Mishra, R.P. Agarwal
DOI :  10.14445/22315381/IJETT-V28P281

Citation 

Shailendra Mishra, Divya Mishra, R.P. Agarwal"Pragmatic Analysis of CNT Interconnects for Nanometer Regime", International Journal of Engineering Trends and Technology (IJETT), V28(9),432-435 October 2015. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

Abstract
The present age of nanometer has made it inevitable to introduce new conventions to meet the ever growing demand of device scaling and circuit minimising. The continuous improvement in electronic circuitry has been assisted by periodic doubling of transistor densities in ICs over the last few decades. However, as every technology, material has its limitation so does the conventional interconnect materials like Cu and Al. Consequently, newer options are being envisaged to meet the current and future demands. To get acquainted with the emerging technologies that assist the incorporation of interconnect subjected to newer technology nodes and extent of integrated circuit scaling, here I review some of them and present as an idea for future advancements for the same.

 References

1) Jack S. Kilby, ?Turning potential into realities: The invention of the Integrated Circuits, Texas Instruments Incorporated, USA, pp. 574-485, 2000.
2) Gordon E. Moore, ?Cramming more components onto integrated circuits, Electronics, Volume 38, Number 8, 1965.
3) Robert H. Dennard et al., ?Design of Ion-Implanted MOSFETs with Very Small Physical Dimensions, IEEE J. Solid State Circuits, pp. 256- 268, 1974.
4) Jussi Putaala,?Reliability and Prognostic monitoring methods of Electronics Interconnections in Advanced SMD Applications, Ph.D. dissertation, Faculty of Information Technology and Electrical engineering, Department of Electrical Engineering, University of Oulu Graduate School, University of Oulu, 2015.
5) Maly, W., "Future of testing: Reintegration of design, testing and manufacturing," in European Design and Test Conference, 1996. ED&TC 96. Proceedings, vol.11, no.14, pp. 19, 1996.
6) M. Haselman, S. Hauck, "The Future of Integrated Circuits: A Survey of Nanoelectronics", Proceedings of the IEEE, Vol. 98, No. 1, pp. 11-38, 2010.
7) Elgamel, M. et al., ? Crosstalk noise analysis in ultra-deep submicrometer technologies," in Interconnect Noise Optimization in Nanometer Technologies, Ist ed., US, Springer,2006, ch. 4, pp. 45-57.
8) Yang, Z.; Mourad, S., "Deep submicron on chip crosstalk [and ANN prediction]," in Instrumentation and Measurement Technology Conference, 1999. IMTC/99. Proceedings of the 16th IEEE, vol.3, pp.1788-1793, 1999.
9) Brajesh Kumar Kaushik, Sankar Sarkar, Rajendra P. Agarwal, and Ramesh C. Joshi ?Crosstalk noise generated by parasitic inductances in System-on-Chip VLSI interconnects HAIT Journal of Science and Engineering B, Volume x, Issue x, pp. 1-17, 2007.
10) Navin Srivastava and Kaustav Banerjee, ?Performance Analysis of Carbon Nanotube Interconnects for VLSI Applications, in Computer- Aided Design, ICCAD-2005. IEEE/ACM International Conference, session 4D.2, pp. 383-390, 2005.
11) Ma, X. & Arce, G. R. Computational Lithography (Wiley, 2011).
12) Bohr, M.T., ?Interconnect scaling-the real limiter to high performance ULSI, in Electron Devices Meeting, 1995. IEDM `95, pp.241-244, 1995.
13) https://en.wikipedia.org/wiki/10_nanometer.
14) Joel Hruska June 23, 2014. 14nm, 7nm, 5nm: How low can CMOS go? It depends if you ask the engineers or the economists.
15) Available:
16) http://www.extremetech.com/computing/184946-14nm-7nm-5nm-howlow- can-cmosgoit-depends-if-you-ask-theengineers-orthe- economists. 17) The International Technology Roadmap For Semiconductors 2007 Edition Interconnect, www.itrs.net.
18) A.K. Goel, High-Speed VLSI Interconnections, 2nd ed. (Wiley- Interscience; IEEE Press, Hoboken, NJ, 2007).
19) A.K. Goel, IEEE Canadian Conference on Electrical and Computer Engineering (CCECE 2008) (Niagara Falls, ON 2008 May 4-7, IEEE) p. 189.
20) http://semimd.com/blog/2014/10/31/airgaps-in-copper-interconnectsfor- logic.
21) J. Gambino, ?Copper Interconnect Technology for the 32 nm node and beyond, Proc. of IEEE Custom Integrated Circuits Conference, CICC ’09, pp.141– 149, Sep 2009.
22) Zhifeng Ren et al., ?Properties and Applications of Aligned Carbon Nnotube Arrays, in Aligned Carbon Nanotubes: Physics, Concepts, Fabrication and Devices, New York, Springer Link (Online service), 2013, ch.8, pp. 232-238. DOI: 10.1007/978-3-642-30490-3_1.
23) http://www.wired.com/2009/12/1223shockley-bardeen-brattaintransistor/
24) Chih-Tang Sah, ?Bipolar Junction Transistor and Other Bipolar Transistor Devices, in Fundamentals of Solid-state Electronics, IVth ed. Singapore, World Scientific Publishing Co. Pte. Ltd., 1994, ch.8, pp. 708.

Keywords
Device scaling, electronmigration, Low-k Dielectrics, porous low-k ILD materials.