Analysis of Leakage Reduction Technique on Different SRAM Cells
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International Journal of Engineering Trends and Technology (IJETT) |  |
| © 2011 by IJETT Journal | ||
| Volume-2 Issue-3 |
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| Year of Publication : 2011 | ||
| Authors : Monika Yadav, Shyam Akashe, Dr.Yogesh Goswami |
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Citation
Monika Yadav, Shyam Akashe, Dr.Yogesh Goswami."Analysis of Leakage Reduction Technique on Different SRAM Cells".International Journal of Engineering Trends and Technology (IJETT),V2(3):78-83 Nov to Dec 2011. ISSN:2231-5381. www.ijettjournal.org. Published by Seventh Sense Research Group.
Abstract
Leakage components is very important for estimation and reduction of leakage power, especiall y for low power applications. This provides the motivation to explore the design of low leakage SRAM cells. High leakage currents in deep submicron regimes are becoming a major contributor to total power dissipation of CMOS circuits as the threshold voltag e, channel length and gate oxide thickness are scaled. Memory leakage suppression is critically important for the success of power - efficient designs, especially for ultra - low power applications. As the channel length of the MOSFET reduces, the leakage cur rent in the SRAM increases. One method is to reduce the standby supply voltage (VDD) to its limit, which is the Data retention voltage (DRV), leakage power can be substantially reduced. Also, lower operating voltage will lower the stability of SRAM cell re sulting in lower value of static no ise margin. To reduce the sub - threshold leakage further, an adaptive voltage level (AVL) circuit is added to this cell, which controls the effective voltage across the SRAM cell in inactive mode. Two schemes are employed; one in which the supply voltage is reduced and the other in which the ground potential is increased. CADENCE Simulations are performed with 90nm CMOS technology process file and the leakage currents of all the cells are measured and compared. Simulation r esults revealed that there is a significant reduction in leakage current for this proposed ce ll with the A VL circuit reducing the supply voltage .
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Keywords
Leakage power, SRAM, leakage reduction techniques