VHDL Design and Implementation for Optimum Delay & Area for Multiplier & Accumulator Unit by 32 Bit Sequential Multiplier

VHDL Design and Implementation for Optimum Delay & Area for Multiplier & Accumulator Unit by 32 - Bit Sequential Multiplier

  ijett-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2012 by IJETT Journal
Volume-3 Issue-5                       
Year of Publication : 2012
Authors :  SARITA SINGH , SACHIN MITTAL

Citation 

SARITA SINGH , SACHIN MITTAL. "VHDL Design and Implementation for Optimum Delay & Area for Multiplier & Accumulator Unit by 32 - Bit Sequential Multiplier". International Journal of Engineering Trends and Technology (IJETT). V3(5):683-686 Sep-Oct 2012. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

Abstract

High performance systems such as microprocessors, di gital signal processors, filters, ALU etc. which is need of hour now days requires a lot of components. One of main component of these high performance systems is multiplier. Most of the DSP computations involve the use of multiply - accumulate operations, a nd therefore the design of fast and efficient multipliers is imperative. However, area and speed are usually conflicting constraints so that improving speed results mostly in larger areas. This thesis investigates analysis of different multiplier for speed , area and delay usage. We try to present an efficient multiplier is produce fast, accurate and require minimum area. In this paper we will first study different types of multipliers: Then we compared the working of different multipliers by comparing the m emory usage, speed and area by each of them. The result of this thesis helps us to choose a better option to choose a better multiplier out of different multipliers in fabricating different systems.

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Keywords
MAC,sequentialmultiplier,VHDL,Dataflow, waveform analyzer .