Implementation of 16x16bit and 32x32bit Vedic Multiplier using FPGA board

Implementation of 16x16bit and 32x32bit Vedic Multiplier using FPGA board

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2016 by IJETT Journal
Volume-42 Number-1
Year of Publication : 2016
Authors : Ms. Ayushi Sharma, Mr. Ajit Singh
DOI :  10.14445/22315381/IJETT-V42P201

Citation 

Ms. Ayushi Sharma, Mr. Ajit Singh "Optimization of Sand Casting Process Parameters for 46MnSi4 Alloy Steel Trash Plate Castings Applicable for Roller Stand", International Journal of Engineering Trends and Technology (IJETT), V42(1),1-5 December 2016. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

Abstract
This paper proposed the implementation of 16x16bit and 32x32bit Vedic Multiplier using modified Ripple Carry Adder, modified Kogge Stone Adder and BRENT KUNG ADDER on Spartan 6 family xc6slx4 -3-tqg144 FPGA and its synthesis using XILINX ISE 14.1 simulator and coding is done using VERILOG HDL. Vedic Mathematics is the ancient system of mathematics which has a unique technique of calculations based on 16 Sutras. The work has proved the efficiency of Urdhva Tiryakbhyam– Vedic method for multiplication which strikes a difference in the actual process of multiplication itself. It enables parallel generation of intermediate products, eliminates unwanted multiplication steps with zeros and scaled to higher bit levels using Karatsuba algorithm with the compatibility to different data types. Urdhva Tiryakbhyam Sutra is most efficient Sutra (Algorithm), giving minimum delay for multiplication of all types of numbers, either small or large.

 References

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Keywords
Kogge Stone Adder, Ripple Carry Adder, BRENT KUNG ADDER, FPGA board, Urdhva Tiryakbhyam, Verilog HDL.