Delay Efficient Kogge Stone Approach for Implementing Shift Registers By Using Pulsed Latches

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2017 by IJETT Journal
Volume-43 Number-2
Year of Publication : 2017
Authors : Somarajupalli sudharani, M.Sumalatha
DOI :  10.14445/22315381/IJETT-V43P219

Citation 

Somarajupalli sudharani, M.Sumalatha "Delay Efficient Kogge Stone Approach for Implementing Shift Registers By Using Pulsed Latches", International Journal of Engineering Trends and Technology (IJETT), V43(2),109-115 January 2017. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

Abstract
This project proposes delay efficient architecture for shift registers by using pulsed latches instead of flip flops. By using latches instead of flip-flops the major factors area and power can be reduced. By considering the necessary delays in pulses for latches the timing problem latches can be reduced. For obtaining these delays counter has to incremented by 1. The proposed kogge stone adder architecture reduces the delay to maximum extent, and produces numerous variations between conventional adder architecture. The synthesis and simulation is carried out using XILINX ISE 12.3i and HDL is developed using VERILOG language.

 References

[1] P. Reyes, P. Reviriego, J. A. Maestro, and O. Ruano, “New protection techniques against SEUs for moving average filters in a radiation environment,” IEEE Trans. Nucl. Sci., vol. 54, no. 4, pp. 957–964, Aug. 2007.
[2] M. Hatamian et al., “Design considerations for gigabit ethernet 1000 base-T twisted pair transceivers,” Proc. IEEE Custom Integr. Circuits Conf., pp. 335–342, 1998.
[3] H. Yamasaki and T. Shibata, “A real-time image-feature-extraction and vector-generation vlsi employing arrayed-shift-register architecture,” IEEE J. Solid-State Circuits, vol. 42, no. 9, pp. 2046–2053, Sep. 2007.
[4] H.-S. Kim, J.-H. Yang, S.-H. Park, S.-T. Ryu, and G.-H. Cho, “A 10-bit column-driver IC with parasitic-insensitive iterative charge-sharing based capacitor-string interpolation for mobile active-matrix LCDs,” IEEE J. Solid-State Circuits, vol. 49, no. 3, pp. 766–782, Mar. 2014.
[5] S.-H. W. Chiang and S. Kleinfelder, “Scaling and design of a 16-megapixel CMOS image sensor for electron microscopy,” in Proc. IEEE Nucl. Sci. Symp. Conf. Record (NSS/MIC), 2009, pp. 1249–1256.
[6] S. Heo, R. Krashinsky, and K. Asanovic, “Activity-sensitive flip-flop and latch selection for reduced energy,” IEEE Trans. Very Large Scale Integer. (VLSI) Syst., vol. 15, no. 9, pp. 1060–1064, Sep. 2007.
[7] S. Naffziger and G. Hammond, “The implementation of the nextgeneration 64 b itanium microprocessor,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2002, pp. 276–504.
[8] H. Partovi et al., “Flow-through latch and edge-triggered flip-flop hybrid elements,” IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 138–139, Feb. 1996.
[9] E. Consoli, M. Alioto, G. Palumbo, and J. Rabaey, “Conditional push-pull pulsed latch with 726 fJops energy delay product in 65 nm CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2012, pp. 482–483.
[10] V. Stojanovic and V. Oklobdzija, “Comparative analysis of masterslave latches and flip-flops for high-performance and low-power systems,” IEEE J. Solid-State Circuits, vol. 34, no. 4, pp. 536–548, Apr. 1999.
[11] J. Montanaro et al., “A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor,” IEEE J. Solid-State Circuits, vol. 31, no. 11, pp. 1703–1714, Nov. 1996.
[12] S. Nomura et al., “A 9.7 mW AAC-decoding, 620 mW H.264 720p 60fps decoding, 8-core media processor with embedded forwardbody- biasing and power-gating circuit in 65 nm CMOS technology,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2008, pp. 262–264.
[13] Y. Ueda et al., “6.33 mW MPEG audio decoding on a multimedia processor,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2006, pp. 1636–1637.
[14] B.-S. Kong, S.-S. Kim, and Y.-H. Jun, “Conditional-capture flip-flop for statistical power reduction,” IEEE J. Solid-State Circuits, vol. 36, pp. 1263–1271, Aug. 2001.
[15] C. K. Teh, T. Fujita, H. Hara, and M. Hamada, “A 77% energy-saving 22-transistor single-phase-clocking D-flip-flop with adaptive-coupling configuration in 40 nm CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2011, pp. 338–339.

Keywords
flip-flops, latches, kogge stone adder, VERILOG.