Design And Simulation Of 10-Bit Pipeline Adc Using Switch Capacitor Circuit And Opamp Sharing In 0.25 µm CMOS Technology at 2.5 V
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International Journal of Engineering Trends and Technology (IJETT) |  |
| © 2017 by IJETT Journal | ||
| Volume-43 Number-3 |
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| Year of Publication : 2017 | ||
| Authors : Deepak Patidar, Mr. Piyush Moghe, Vijay Sharma |
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| DOI : 10.14445/22315381/IJETT-V43P225 |
Citation
Deepak Patidar, Mr. Piyush Moghe, Vijay Sharma "Design And Simulation Of 10-Bit Pipeline Adc Using Switch Capacitor Circuit And Opamp Sharing In 0.25 µm CMOS Technology at 2.5 V", International Journal of Engineering Trends and Technology (IJETT), V43(3),151-157 January 2017. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
Abstract
A 10-bit pipeline Analog-to-digital Converter (ADC) is designed using switched capacitor circuit. ADC is designed in 9 stages, 1.5 bit/stage pipeline is used in eight stages and ninth stage uses two bit flash ADC. The ADC uses Opamp sharing techniques which are shared between amplifying and MDAC stage. Load capacitance has been removed which reduced the number of capacitors used and power consumption. The ADC is designed on 0.25 µm CMOS technology at 2.5 V supply voltage. S/H is used in first stages that consume most of the power consumed by the ADC, after first stage S/H circuit is removed, and also the scaling is done to reduce the power consumption. Cascodeopamp is designed with gain of 72.52 dB, phase margin of 66º and unity gain bandwidth of 162.61MHz. The ADC is designed at sampling rate of 5 MS/s and consumes 158.1208mWpower.
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Keywords
ADC, MDAC, sample and hold, pipeline ADC, DAC.