A novel majority gate approach for implementing efficient qca comparator
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International Journal of Engineering Trends and Technology (IJETT) |  |
| © 2017 by IJETT Journal | ||
| Volume-43 Number-6 |
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| Year of Publication : 2017 | ||
| Authors : Tiru Sameer Yarlagadda, GSAJ Manikumar |
Citation
Tiru Sameer Yarlagadda, GSAJ Manikumar " A novel majority gate approach for implementing efficient qca comparator ", International Journal of Engineering Trends and Technology (IJETT), V43(6),320-327 January 2017. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
Abstract
A quantum-dot cellular automaton (QCA) was an attractive technology now a days which is used in developing ultra-dense-low-power high-performance digital circuits. Many solutions have been proposed recently for several arithmetic circuits, such as adders, multipliers, and comparators. Nevertheless, since the design of digital circuits in QCA still poses many challenges, novel implementation strategies and methodologies are highly wished for as being an attractive. This paper put forward a new design approach aligned to the implementation of binary comparators in QCA. New formulations of basic logic equations which are required to perform the comparison function is proposed. The new scheme has been exploited in designing two different comparator architectures and for several operands word length. With comparison to existing counterparts, the comparators proposed in this project exhibit significantly higher speed and reduced overall area. In The proposed scheme, we deal with 32-bit numbers which have less number of resources unlike conventional comparators, by which the realization of low power and area efficient comparator is designed. This comparator can be used widely in central processing units (CPUs) and microcontrollers.
References
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Keywords
This comparator can be used widely in central processing units (CPUs) and microcontrollers.