Clock-Gated Pseudo Random Number Generator with Programmable Polynomial Taps using Clock- Gated Linear Feedback Shift Register (LFSR)
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International Journal of Engineering Trends and Technology (IJETT) |  |
| © 2017 by IJETT Journal | ||
| Volume-45 Number-5 |
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| Year of Publication : 2017 | ||
| Authors : N.Sreenivasa Rao,M.Sai Praveena, M.Sravani, O.Renuka Devi, V.Lavanya |
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| DOI : 10.14445/22315381/IJETT-V45P243 |
Citation
N.Sreenivasa Rao,M.Sai Praveena,M.Sravani,O.Renuka Devi,V.Lavanya "Clock-Gated Pseudo Random Number Generator with Programmable Polynomial Taps using Clock- Gated Linear Feedback Shift Register (LFSR)", International Journal of Engineering Trends and Technology (IJETT), V45(5),207-210 March 2017. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
Abstract
LFSR have the feature of accepting 32bit programmable polynomial and it has a feature of 32 bit or 16 bit LFSR. It has clock gated flip-flop and can be used in dynamic power reduction. This gating of the clock will depend on the previous input and the present input. This “pseudo random number generator” generates 32-bit random number according to the polynomial which is programmable through the input “poly [31:0]”. The top module passes the inputs to the “gated_lfsr” module. The reason for making a top module on top of a “gated_lfsr” is for the flexibility to add multiple “gated_lfsr” in future by just instantiating multiple modules in the top module “pseudo_top”. The “gated_lfsr’ module, in turn, instantiates total “32” multiplexers and “32” “gated d-flip-flops” to output 32-bit pseudo-random number.The “gated d-flip-flop” is a special type of “d-flip-flop’ which has a capability of disabling clock when both the present state and the next state of the d-flip-flop are same, thus saving the dynamic power consumed due to the transitions of the clock signal.
References
[1] Wikipedia, Pseudorandom Number Generators, http://wikipedia.com. Pseudorandom number generator (2003). [2] F. James, “A Review of Pseudo-random Number Generators, “ Computer physics communication 60,1990.
[3] David B. Thomas, Wayne Luk, ?The LUT-SR Family of Uniform Random Number Generators for FPGA Architectures? IEEE transactions on very large scale integration (VLSI) systems, vol. 21, no. 4, April 2013
[4] Carlos Arturo Gayoso, C. González, L. Arnone, M. Rabini, Jorge Castiñeira Moreira, ?Pseudorandom Number Generator Based on the Residue Number System and its FPGA Implementation? 2013 Argentine School of Micro-Nanoelectronics, Technology, and Applications.
Keywords
LFSR, Gated D-FlipFlop, Multiplexer, Polynomial Taps.