IJBTT

Performance Evaluation in Adiabatic Logic Circuits for Low Power VLSI Design

	International Journal of Engineering Trends and Technology (IJETT)
	© 2017 by IJETT Journal
	Volume-45 Number-5
	Year of Publication : 2017
	Authors : Tabassum Ara, Amrita Khera
	DOI :  10.14445/22315381/IJETT-V45P250

Citation 

Tabassum Ara, Amrita Khera "Performance Evaluation in Adiabatic Logic Circuits for Low Power VLSI Design", International Journal of Engineering Trends and Technology (IJETT), V45(5),241-245 March 2017. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

Abstract
As the in semiconductor industries progress by following Moore’s law faithfully from last five decades, and integrating more transistors along with functional circuits on a single chip periodically with every coming process technology. However, this progress help in rapid run towards tiny, circuit design high speed and economical VLSI (Very Large Scale of Integration) circuits has added to excessive power dissipation of numerous circuits used today. In this research paper we have study the different topologies of adiabatic logic such as ECRL, 2N-2N2P and PFAL. The main objective of this paper is to calculate the power consumption, Delay and PDP of the existing adiabatic logic families, and thus compare for the effectiveness in terms of lower power dissipation. All simulations were performed by using HSPICE Simulator at 65nm technology having 10MHz frequency at supply voltage is 1V, for proper validation and verification of the results W/L ratio of all the circuit is kept constant.

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Keywords
C-CMOS, ECRL, 2N-2N2P, Power, Delay.