A Novel Approach for Improvement of Power and Delay on Various Domino Logic Circuits

A Novel Approach for Improvement of Power and Delay on Various Domino Logic Circuits

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2017 by IJETT Journal
Volume-45 Number-9
Year of Publication : 2017
Authors : Jyoti Shrivastava, Paresh Rawat

Citation 

Jyoti Shrivastava, Paresh Rawat "A Novel Approach for Improvement of Power and Delay on Various Domino Logic Circuits", International Journal of Engineering Trends and Technology (IJETT), V45(9),454-460 March 2017. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

Abstract
Leakage power consumption is a major technical problem facing in nanometre CMOS circuit in deep submicron technology. Domino logic is a CMOS based evolution of the dynamic logic techniques based on either PMOS or NMOS transistors. Dynamic logic circuits are used for their high performance, but their high noise and extensive leakage has caused some problems for these circuits. Dynamic CMOS circuits are inherently less resistant to noise than static CMOS circuits. In this paper we proposed different domino logic styles which increases performance compared to existing domino logic styles. According to the simulations in HSPICE at 90nm and 65nm CMOS technology, the proposed circuit shows the improvement of Average power consumption upto for 8 input OR gate 30% compared existing domino logics. This control circuit produces small voltage at the source of the pull down network in the standby mode. It improves the noise immunity of the domino circuits. The performance of these circuits has been evaluated by HSPICE using a BSIM4. Finally average power dissipation characteristics are plotted with the help of a graph and comparisons are made between different logic families.

 References

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Keywords
Low Power, High Speed, CKD, UNG.