Low Power Consumption in 11t SRAM Design by using CMOS Technology
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International Journal of Engineering Trends and Technology (IJETT) |  |
| © 2017 by IJETT Journal | ||
| Volume-45 Number-10 |
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| Year of Publication : 2017 | ||
| Authors : Amit Namdev, PareshRawat |
Citation
Amit Namdev, PareshRawat "Low Power Consumption in 11t SRAM Design by using CMOS Technology", International Journal of Engineering Trends and Technology (IJETT), V45(10),524-530 March 2017. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
Abstract
Ever since the concept of miniaturization took off, process voltage and temperature variations have become the prominent issues because of device scaling. Ranging from electronic devices like smart phones, tablets, multimedia devices like iPod to digital televisions, servers and networking SRAM is being used almost everywhere. It gives the scope of optimizing existing SRAM Topologies to meet the increasing market demand. In this paper CMOS technology is used for SRAM cells in different topology and a proposed 11T SRAM cell are analysed with the other (N)T SRAM cells Proposed circuit shows maximum saving of dynamic power in NB and RB is to 82.21% and 90.57% in 10T, maximum leakage power saving in NB and RB mode is 57.53%, 61.35% at 250C and 45.13%, 48.52 at 1100C in 9T SRAM. Proposed 11T is better in term of power, delay and stability than other existing circuits. Simulation is done by using HSPICE at 32nm CMOS technology in Not Biased (NB) and Reverse Biased (RB) mode with VDD =1V for fair comparison of results.
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Keywords
CMOS, Low power consumption, Shorter Channel Effect, NB and RB mode.