Leakage Power Reduction Techniques for Nanoscale CMOS VLSI Systems and Effect of Technology Scaling on Leakage Power

Leakage Power Reduction Techniques for Nanoscale CMOS VLSI Systems and Effect of Technology Scaling on Leakage Power

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2017 by IJETT Journal
Volume-46 Number-6
Year of Publication : 2017
Authors : P.Prashanti, A.Shravya, K.Dhruthi Vasista, U.Pranathi, G.SriKalyani
DOI :  10.14445/22315381/IJETT-V46P254

Citation 

P.Prashanti, A.Shravya, K.Dhruthi Vasista, U.Pranathi, G.SriKalyani "Leakage Power Reduction Techniques for Nanoscale CMOS VLSI Systems and Effect of Technology Scaling on Leakage Power", International Journal of Engineering Trends and Technology (IJETT), V46(6),309-315 April 2017. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

Abstract
The rise in technology has demanded the use of more and more components on chip. This rise has led to rise in power dissipation and a major challenge for circuit designers.Due to scaling, the reduction of threshold voltage in CMOS circuits increases the sub threshold leakage current which leads to the static power dissipation. It has been observed that leakage power is the major contributor for power dissipation and directly affecting the battery life of circuits.In order to restrain thisleakage power, a comprehensive study and analysis of various leakage power reduction techniques have been presented in this paper. Also the effect of technology scaling on the leakage power is analysed. MICROWIND tool is used for this approach to analyse the power dissipation at different technologies such as 50nm, 90nm, 120nm and 180nm at a given power supply.

 References

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Keywords
leakage power, low powerconsumption, LECTOR, Technology scaling.