Design of PI controller for seven level symmetrical MLI with minimal quantity of switches plus snubber circuit
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International Journal of Engineering Trends and Technology (IJETT) | 
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| © 2017 by IJETT Journal | ||
| Volume-47 Number-8 |
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| Year of Publication : 2017 | ||
| Authors : R.Venkateswara rao, K. Ramash Kumar, V S N Narasimha Raju |
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| DOI : 10.14445/22315381/IJETT-V47P273 |
Citation
R.Venkateswara rao, K. Ramash Kumar, V S N Narasimha Raju "Design of PI controller for seven level symmetrical MLI with minimal quantity of switches plus snubber circuit", International Journal of Engineering Trends and Technology (IJETT), V47(8),445-452 May 2017. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group
Abstract
In the current days, multilevel inverters (MLIs) are very popular in industrial applications. The main problems of MLIs are large size (i.e. high cost) and high switching losses (i.e. voltage stress). In this article studies on a design and implementation of classical proportional integral (PI) controller for seven level symmetrical MLI (SLSMLI) with minimum number of switches plus snubber circuit. The classical linear proportional P controller is not able to regulate the output voltage of MLI particularly in larger line and load disturbances. In order to regulate the output voltage, minimize the switching losses, reduce the size and cost of MLI, a PI controller for seven levels symmetrical MLI with reduced quantity of switches plus snubber circuit (SC) is designed. Here, inverted sine carrier variable frequency (ISCVFPWM) technique is used to generate the PWM pulses for designed MLI switches. The performance of designed model is investigated at different working states by making the MATLAB/Simulink model in comparison with P controller. The simulation results of designed MLI have produced minimized total harmonic distortion (THD), excellent output voltage/output current regulations and good power factor.
References
1. D. Mohan and S. B.Kurub, ?Performance analysis of SPWM control strategies using 13 level cascaded MLI, in IEEE International Conference on Advances in Engineering Science & Management (ICAESM’12).
2. T. V. V. S. Lakshmi, N. George, S. Umashankar, and D. P. Kothari, Cascaded seven level inverter with reduced number of switches using level shifting PWM technique, International Conference on Power, Energy and Control(ICPEC’13),pp.676– 680,February2013.
3. J. Rodr´?guez, J.-S. Lai, and F. Z. Peng, ?Multilevel inverters: a survey of topologies, controls, andapplications,IEEETransactionsonIndustrialElectronics, vol.49, no.4, pp.724–738, 2002.
4. O.L.Jimenez, R.A.Vargas, J.Aguayo, J.E.Arau, G.Vela, and A.Claudio, ?THD in cascade multi-level inverter symmetric and asymmetric, in Proceedings of the IEEE Electronics, Robotic sand Automotive Mechanics Conference (CERMA ’11), pp. 289–295, November2011.
5. P.PalanivelandS.S.Dash, ?Analysis of THD and output voltage performance for cascaded multilevel inverter using carrier pulse width modulation techniques, IET Power Electronics, vol. 4, no.8, pp.951–958, 2011.
6. Babaei and S. H. Hosseini, ?New cascaded multilevel inverter topology with minimum number of switches, Energy Converse. Manage, vol. 50, no. 11, pp. 2761–2767, Nov. 2009.
7. Gregory, D. Patangia, H. ?A Novel Multilevel Strategy in SPWM Design? Industrial Electronics, IEEE International Symposium, ISIE 2007, pp.515-520.
Keywords
Multilevel inverter, Carrier Based PWM, MATALAB/Simulink, Snubber Circuit.