Implementation of Low Power RISC Based Flexible DSP Processor

Implementation of Low Power RISC Based Flexible DSP Processor

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2017 by IJETT Journal
Volume-49 Number-3
Year of Publication : 2017
Authors : Reena Ramadevi T, Raghavaiah B
DOI :  10.14445/22315381/IJETT-V49P230

Citation 

Reena Ramadevi T, Raghavaiah B "Implementation of Low Power RISC Based Flexible DSP Processor", International Journal of Engineering Trends and Technology (IJETT), V49(3),186-191 July 2017. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

Abstract
The computers that which uses simple algorithms for solving the problems such machines are called as the Reduced Instruction Set Computers. A processor must have the capability of performing arithmetic logical operations and the capability of transferring the data. The major blocks of the processor are Program counter (PC), Flexible computational unit (FCU), Control unit (CU), Accumulator, Instruction register (IR), Memory and additional logic. RISC in fact enhances the performance of processor by taking into consideration the factors like simple architecture construction and instruction set, easy instruction set for decoding and simplified control architecture. With the use of Peres reversible logic gates in the proposed processor having RISC 32 bit wide architecture there may be size reduction when compare with the conventional architecture based on carry save logic adder approach. The RTL (Register transfer level) is designed based on VERILOG and the simulation and synthesis is performed by XILINX ISE 12.3i.

 References

[1] P. Ienne and R. Leupers, Customizable Embedded Processors: Design Technologies and Applications. San Francisco, CA, USA: Morgan Kaufmann, 2007.
[2] P. M. Heysters, G. J. M. Smit, and E. Molenkamp, “A flexible and energy-efficient coarse-grained reconfigurable architecture for mobile systems,” J. Supercomput., vol. 26, no. 3, pp. 283–308, 2003.
[3] B. Mei, S. Vernalde, D. Verkest, H. D. Man, and R. Lauwereins, “ADRES: An architecture with tightly coupled VLIW processor and coarse-grained reconfigurable matrix,” in Proc. 13th Int. Conf. Field Program. Logic Appl., vol. 2778. 2003, pp. 61–70.
[4] M. D. Galanis, G. Theodoridis, S. Tragoudas, and C. E. Goutis, “A high-performance data path for synthesizing DSP kernels,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 25, no. 6, pp. 1154–1162, Jun. 2006.
[5] K. Compton and S. Hauck, “Automatic design of reconfigurable domainspecific flexible cores,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 16, no. 5, pp. 493–503, May 2008.
[6] S. Xydis, G. Economakos, and K. Pekmestzi, “Designing coarse-grain reconfigurable architectures by inlining flexibility into custom arithmetic data-paths,” Integr., VLSI J., vol. 42, no. 4, pp. 486–503, Sep. 2009.
[7] S. Xydis, G. Economakos, D. Soudris, and K. Pekmestzi, “High performance and area efficient flexible DSP datapath synthesis,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 3, pp. 429–442, Mar. 2011.

Keywords
RISC, Reversible logic gates, Carry save logic, XILINX.