Comparitive Study Of Diffrent Multiplier Architectures

Comparitive Study Of Diffrent Multiplier Architectures

  ijett-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2013 by IJETT Journal
Volume-4 Issue-10                      
Year of Publication : 2013
Authors : Prashant Kumar Sahu , Prof. Nitin Meena

Citation 

Prashant Kumar Sahu , Prof. Nitin Meena. "Comparitive Study Of Diffrent Multiplier Architectures". International Journal of Engineering Trends and Technology (IJETT). V4(10):4293-4297 Oct 2013. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group.

Abstract

This paper presents a comparative analysis of three different multiplier architectures. The three multipliers architecture are array multiplier, a column bypass multiplier, and a array multiplier using Reversal Logic schemes. The multipliers are implemented on Spartan 6 FPGA. The architectures are compared in terms of critical path delay, power dissipation and area. The different multipliers are compared in terms of dynamic power consumption due to the scaling effects on leakage current. Each of the three multipliers has its own trade-offs between power and delay.

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Keywords
Low Power, Multiplier, Switching Delay, bypassing techniques, reversible logic.