Design of Energy Efficient Arithmetic Circuits Using Charge Recovery Adiabatic Logic

  ijett-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
© 2013 by IJETT Journal
Volume-4 Issue-1                       
Year of Publication : 2013
Authors : B. Dilli Kumar , M. Bharathi


B. Dilli Kumar , M. Bharathi. "Design of Energy Efficient Arithmetic Circuits Using Charge Recovery Adiabatic Logic". International Journal of Engineering Trends and Technology (IJETT). V4(1):32-40 Jan 2013. ISSN:2231-5381. published by seventh sense research group


Low power has emerge d as a principle theme in today electronic industry. Energy efficiency is one of the most important features of modern electronic systems designed for high speed and portable applications. The power consumption of the electronic devices can be reduced by adopting different design styles. Adiabatic logic style is said to be an attractive solution for such low power electronic applications. This paper presents an energy efficient technique for digital circuits that uses adiabatic logic. The proposed technique has less power dissipation when compared to the conventional CMOS design style. This paper evaluates the full adder in different adiaba tic logic styles and their results were compared with the conventional CMOS design. The simulation results indicate that t he proposed technique is advantageous in many of the low power digital applications.


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Adiabatic, Charge recovery, low power, energy efficient, digital circuits, sinusoidal power clock .