Proposed Multi Level Cache Models Based on Inclusion & Their Evaluation

  ijett-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2013 by IJETT Journal
Volume-4 Issue-7                      
Year of Publication : 2013
Authors : Megha Soni , Rajendra Nath

Citation 

Megha Soni , Rajendra Nath. "Proposed Multi Level Cache Models Based on Inclusion & Their Evaluation". International Journal of Engineering Trends and Technology (IJETT). V4(7):2945-2951 Jul 2013. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group.

Abstract

The performance of a multi - level cache hierarchy is decided by the number of cache levels following the inclusion or mutual exclusion property. Making all the cache levels in a hierarchy to behave either as inclusive or exclusive is not much beneficial. Significant performance improvement is possible if some of the cache levels are made to follow inclusion property while others not. Different cache design models are possible under this situation. This paper presents two proposed cache design models in a three level cache hierarchy. Our first proposed cache model involves making level1 and level2 as exclusive and level3 as inclusive with both of them. In second proposed cache model, level1 and level2 are taken as inclusiv e and level3 is taken as exclusive with level2. Both the proposed cache models have been experimentally evaluated and compared on six evaluation parameters using simulator which has been implemented in PHP - 5.3. Proposed cache model 2 has been found to giv e better overall performance than proposed cache model 1.

References

[1] J.L. Baer and W.H. Wang, “On the inclusion properties for multi - level cache hierarchies,” In ISCA - 10, pp. 73 – 80, 1988.
[2] K. Fletcher, W. E. Speight, and J. K. Bennett, “Techniques for Reducing the Impact of Inclu sion in Shared Network Cache Multiprocessors,” Rice ELEC TR 9413, 1995.
[3] N. P. Jouppi, “Improving direct - mapped cache performance by the addition of a fully associative cache and pre - fetch buffers,” In ISCA, 1990.
[4] A. Jaleel, E. Borch, M. Bhandaru, S. C. Ste ely Jr., and J. Emer, “Achieving non - inclusive cache performance with inclusive caches: Temporal Locality Aware (TLA) cache management policies,” In MICRO - 43, MICRO ’43, 2010.
[5] Junlin Lu, Xu Cheng, Zichao Xie, Lingda Li, Dong Tong, “Improving inclusive cach e performance with two - level eviction priority,” In IEEE 30th International Conference on Computer Design (ICCD), pp. 387 - 392, 2012.
[6] T. M. Wong and John Wilkes, “My cache or yours? Making storage more exclusive,” USENIX Annual Technical Conference, pp. 16 1 – 175, 10 – 15 June 2002.
[7] B. S. Gill, “On Multi - level Exclusive Caching: Of fline Optimality and Why promotions are better than demotions,” FAST`08 Proceedings of the 6th USENIX Conference on File and Storage Technologies, No. 4, 2008.
[8] J. Gaur, M. Chaudhuri, S. Subramoney, “Bypass and insertion algorithms for exclusive last - level caches,” ISCA - 38, 2011.
[9] S. Gupta, H. Gao, H. Zhou, “Adaptive Cache Bypassing for Inclusive Last Level Caches,” 2012.
[10] Zheng, Ying, Brian T. Davis, and Matthew Jordan, “Performance eval uation of exclusive cache hierarchies,” In Performance Analysis of Systems and Software, 2004 IEEE International Symposium on - ISPASS, pp. 89 - 96, 2004.

Keywords
cache memory, inclusive, exclusive, multi - level cache.