Design and Implementation of High Speed Carry Select Adder

  ijett-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
© 2013 by IJETT Journal
Volume-4 Issue-9                      
Year of Publication : 2013
Authors :  P.Prashanti , Dr. B.Rajendra Naik


P.Prashanti , Dr. B.Rajendra Naik. "Design and Implementation of High Speed Carry Select Adder". International Journal of Engineering Trends and Technology (IJETT). V4(9):3985-3990 Sep 2013. ISSN:2231-5381. published by seventh sense research group.


Design of area and power - efficient high - speed data path logic systems are one of the most substantial areas of research in VLSI system design. In digital adders, the speed of addition is limited by the time required to propagate a carry through the adder. Carry Select Adder (CSLA) is one of the fastest adders used in many data - processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. Th is work uses a simple and efficient gate - level modification to significantly reduce the area and power of the CSLA. The CSLA is used in many computational systems to alleviate the problem of carry propagation delay by independently generating multiple carr ies and then select a carry to generate the sum. However, the CSLA is not area efficient because it uses multiple pairs of Ripple Carry Adders (RCA) to generate partial sum and carry by considering carry input Cin = 0 and Cin = 1, then the final sum and c arry are selected by the multiplexers (mux). This is modified by replacing the RCA with Cin=1 with BEC in the regular CSLA to achieve low area and power consumption. But there is a slight increase in the delay. The delay can be reduced by improving the CSL A by replacing a D - Latch in place of RCA with Cin = the regular CSLA to achieve high speed addition. The performance of this CSLA is evaluated by implementing an FIR Filter by using the CSLA in the adder part. This work focuses on the performance of C SLA in terms of delay and power and it is found that CSLA is a high speed and low power adder.


[1] B. Ramkumar and Harish M Kittur, “ Low Power and Area Efficient Carry Select Adder ” IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS - 2011.
[2] Bedrij, O. J., (1962), “ Carry - selec t adder ,” IRE Trans. Electron. Comput., pp.340 – 344 .
[3] Ceiang ,T. Y. and Hsiao,M. J. ,( Oct. 1998 ),“ Carry - select adder using single ripple carry adder ,” Electron. Lett., vol. 34, no. 22, pp. 2101 – 2103
[4] Ramkumar,B. , Kittur, H.M. and Kannan ,P. M. ,(2010 ),“ ASIC implementation of modified faster carry save adder ,” Eur. J. Sci. Res., vol. 42, no. 1,pp.53 – 58 ,2010 .
[5] J. M. Rabaey , Digtal Integrated Circuits — A Design Perspective . Upper Saddle River, NJ: Prentice - Hall, 2001.
[6] E. Abu - Shama and M. Bayoumi, “ A New cell for low power adders ,” in Proc.Int. Midwest Symp. Circuits and Systems, 1995, pp. 1014 – 1017
[7] Y. Kim and L. - S. Kim, “ 64 - bit carry - select adder with reduced area ,” Electron. Lett., vol. 37, no. 10, pp. 614 – 615, May 2001.
[8] Y. He, C. H. Chang, and J. Gu, “ An area efficient 64 - bit square root carry - select adder for low power applications ,” in Proc. IEEE Int. Symp. Circuits Syst., 2005, vol 4, pp.4082 - 4085.
[9] Oklobdzija. V. G, “High Speed VLSI Arithmetic Units: Adders and Multipliers” , in “Design of High Performance Microprocessor Circuits”, Book edited by A.Chandrakasan, IEEE Press,2000.
[10] Kaushik Roy, Sharat C. Prasad (2000), “Low - Power CMOS VLSI Circuit Design”, John Wiley & Sons, Inc.

CSLA, D - Latch, low power