Design and implementation of DDA architecture for FIR Filters
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International Journal of Engineering Trends and Technology (IJETT) | 
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| © 2013 by IJETT Journal | ||
| Volume-4 Issue-9 |
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| Year of Publication : 2013 | ||
| Authors : T. Ranjith Kumar |
Citation
T. Ranjith Kumar. "Design and implementation of DDA architecture for FIR Filters". International Journal of Engineering Trends and Technology (IJETT). V4(9):4123-4127 Sep 2013. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group.
Abstract
Traditionally, direct implementat ion of a K - tap FIR filter requires K multiply - and - accumulate (MAC) blocks, which are expensive to implement in FPGA due to logic complexity and resource usage. To resolve this issue, we first presen t DA, which is a architecture without multiplier . This pa per implements the DA architecture. This architecture is applicable to only one type of filter Coefficients i.e., fixed filter coefficient. In case if we want to operate on variable filter coefficients we have been using Dynamic Distributed Arith metic (DDA ) Architecture. In this we are provi ding the flexibility to operate on variable filter coefficients. Here also compare DA( Distributed Arithmetic ),D - DA(Decomposed - Distributed Arithmetic ),DDA(Dynamic Distributed Arithmetic) by using of XILINX ISE 9.1.i tool, for simulation and synthesis, dumping on sparton - 3E FPGA.
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Keywords
Distrib uted Arithmetic; FIR; Decomposed DA; dynamic DA.