32 bit×32 bit Multiprecision RazorBased Dynamic Voltage Scaling Multiplier with Operands Scheduler

32 bit×32 bit Multiprecision Razor-Based Dynamic Voltage Scaling Multiplier with Operands Scheduler

  IJETT-book-cover  International Journal of Engineering Trends and Technology (IJETT)          
  
© 2017 by IJETT Journal
Volume-50 Number-4
Year of Publication : 2017
Authors : Mr.M Basha, Mr.V Leelashyam
DOI :  10.14445/22315381/IJETT-V50P238

Citation 

Mr.M Basha, Mr.V Leelashyam "32 bit×32 bit Multiprecision Razor-Based Dynamic Voltage Scaling Multiplier with Operands Scheduler", International Journal of Engineering Trends and Technology (IJETT), V50(4),234-237 August 2017. ISSN:2231-5381. www.ijettjournal.org. published by seventh sense research group

Abstract
Multiplication is the basic arithmetic operation. In DSP (digital signal processing) a lot of arithmetic operations require the use of multiplications. The performance of 3D computer graphics, gaming, Embedded systems, DSP etc, are particularly depends on the performance of multiplication steps. Multipliers have more area, long latency and consume high amount of power. Critical factors in the design of multipliers are chip area and speed of multiplication and require less hardware. Scaling of technology node increases power-density more than expected. This paper is focused on Multi Precision (MP) reconfigurable multiplier combined with various precision methods, parallel processing (PP), razor-based dynamic voltage scaling (DVS), and MP operands scheduling to give optimum level of performance for various operating conditions. Adapting to the run-time workload of the targeted application, razor flip-flops combine with a dithering voltage unit, because of this the multiplier is able to achieve the lowest power consumption. Use of single switch dithering voltage unit and razor flip-flops help to minimize the safety margins in voltage and overhead in DVS. The more amount of silicon area and power requirements are reduced because of reconfigurable structures.

Reference
[1] R. Min, M. Bhardwaj, S.-H. Cho, N. Ickes, E. Shih, A. Sinha, A. Wang, and A. Chandrakasan, “Energy-centric enabling technologies for wireless sensor networks,” IEEE Wirel. Commun., vol. 9, no. 4, pp. 28–39, Aug. 2002.
[2] M. Bhardwaj, R. Min, and A. Chandrakasan, “Quantifying and enhancing power awareness of VLSI systems,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 9, no. 6, pp. 757–772, Dec. 2001.
[3] A. Wang and A. Chandrakasan, “Energy-aware architectures for a realvalued FFT implementation,” in Proc. IEEE Int. Symp. Low Power Electron. Design, Aug. 2003, pp. 360–365.
[4] T. Kuroda, “Low power CMOS digital design for multimedia processors,” in Proc. Int. Conf. VLSI CAD, Oct. 1999, pp. 359–367.
[5] H. Lee, “A power-aware scalable pipelined booth multiplier,” in Proc. IEEE Int. SOC Conf., Sep. 2004, pp. 123–126.
[6] S.-R. Kuang and J.-P. Wang, “Design of power-efficient configurable booth multiplier,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 3, pp. 568–580, Mar. 2010.
[7] O. A. Pfander, R. Hacker, and H.-J. Pfleiderer, “A multiplexer-based concept for reconfigurable multiplier arrays,” in Proc. Int. Conf. Field Program. Logic Appl., vol. 3203. Sep. 2004, pp. 938–942.
[8] F. Carbognani, F. Buergin, N. Felber, H. Kaeslin, and W. Fichtner, “Transmission gates combined with level-restoring CMOS gates reduce glitches in low-power low-frequency multipliers,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 16, no. 7, pp. 830–836, Jul. 2008.
[9] T. Yamanaka and V. G. Moshnyaga, “Reducing multiplier energy by data-driven voltage variation,” in Proc. IEEE Int. Symp. Circuits Syst., May 2004, pp. 285–288.
[10] W. Ling and Y. Savaria, “Variable-precision multiplier for equalizer with adaptive modulation,” in Proc. 47th Midwest Symp. Circuits Syst., vol. 1. Jul. 2004, pp. I-553–I-556.
[11] K.-S. Chong, B.-H. Gwee, and J. S. Chang, “A micropower low-voltage multiplier with reduced spurious switching,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 2, pp. 255–265, Feb. 2005.
[12] M. Sjalander, M. Drazdziulis, P. Larsson-Edefors, and H. Eriksson, “A low-leakage twin-precision multiplier using reconfigurable power gating,” in Proc. IEEE Int. Symp. Circuits Syst., May 2005, pp. 1654–1657.
[13] S.-R. Kuang and J.-P. Wang, “Design of power-efficient pipelined truncated multipliers with various output precision,” IET Comput. Digital Tech., vol. 1, no. 2, pp. 129–136, Mar. 2007.
[14] J. L. Holt and J.-N. Hwang, “Finite precision error analysis of neural network hardware implementations,” IEEE Trans. Comput., vol. 42, no. 3, pp. 281–290, Mar. 1993.
[15] A. Bermak, D. Martinez, and J.-L. Noullet, “High-density 16/8/4-bit configurable multiplier,” Proc. Inst. Electr. Eng. Circuits Devices Syst., vol. 144, no. 5, pp. 272–276, Oct. 1997.
[16] T. Kuroda, “Low power CMOS digital design for multimedia processors,” in Proc. Int. Conf. VLSI CAD, Oct. 1999, pp. 359–367.
[17] T. D. Burd, T. A. Pering, A. J. Stratakos, and R. W. Brodersen, “A dynamic voltage scaled microprocessor system,” IEEE J. Solid-State Circuits, vol. 35, no. 11, pp. 1571–1580, Nov. 2000.
[18] T. Kuroda, K. Suzuki, S. Mita, T. Fujita, F. Yamane, F. Sano, A. Chiba, Y. Watanabe, K. Matsuda, T. Maeda, T. Sakurai, and T. Furuyama, “Variable supply-voltage scheme for low-power highspeed CMOS digital design,” IEEE J. Solid-State Circuits, vol. 33, no. 3, pp. 454–462, Mar. 1998.

Keywords
Multiplier, Razor Flip Flops, Operand Scheduler, Multiplicand, Multi precision, Dynamic Voltage Scaling.